wilamowski-b-m-irwin-j-d-industrial-communication-systems-2011

Media 2-5
Single ended
Differential
D
D
R
R
R
R
FIGURE 2.5
Multidrop topology.
Single ended
Differential
D
D
D
R R R
D
D
R
D
R
R
FIGURE 2.6
Multipoint topology.
topology is the half-duplex topology, which consists of two driver/receiver pairs that transmit and receive
signals between two points over a single interconnect. Since sharing of a single interconnect requires
that only one transmitter is active at any time, a full-duplex topology implying concurrent transmission
in both directions has to be realized with two lines in parallel.
Physical connection of multiple drivers and receivers to a common signal line raises a design challenge
mainly encountered by impedance discontinuities that device loading and device connections
(stubs) introduce on the common bus.
The topologies presented above can be used with single line or multiple lines in parallel, which correspondingly
increases the rate of transferred bits. On the other hand, parallel lines increase the cost because
of the need of parallel transmitters and receivers and of cable cost according to the cable length. Parallel
data transmission moreover requires provisions for synchronous data clocking, which is basically implemented
by a separate clock line. These aspects are responsible for mostly using single or very few parallel
lines in communication networks with larger line lengths. In this case, a separate clock line can be saved
and replaced by coding techniques allowing for synchronizing the receiver clock as described as follows.
2.2.5 Bit Encoding
For bit transmission, a frame is serialized and sent across a communications link to the destination. As
defined by the open systems interconnection (OSI) model, the physical layer (Layer 1) defines the representation
of each bit as a voltage, current, phase, or frequency. The following basic schemes are used:
• Return to zero, RZ (pulse signaling)
• Non–return to zero transmission, NRZ (level signaling)
• Manchester encoding or Manchester phase encoding (edge/phase signaling)
In earlier transmission techniques, pulses were used to represent bits, e.g., RZ in which a logic 1 is
represented by a pulse and a logic 0 by the absence of a pulse. In NRZ transmission, each data bit is represented
by a level. A high level may represent a logic 1 and a low level a logic 0, or vice versa.
Manchester encoding (Figure 2.7) uses a still different scheme where a logic 1 is represented by a
transition in a particular direction (usually a rising edge) in the centre of each bit. A transition in the
opposite direction (downward in this case) is used to represent a logic 0. Compared with NRZ, advantage
of this coding is that the bit timing is intrinsically indicated by the edges characterizing the bits.
© 2011 by Taylor and Francis Group, LLC