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INTERBUS 33-9<br />

4.5<br />

4<br />

3.5<br />

PL = 1 byte<br />

PL = 4 byte<br />

3<br />

T IB (ms)<br />

2.5<br />

2<br />

1.5<br />

1<br />

0.5<br />

0<br />

0 25 50 75 100 125 150<br />

Number of nodes k<br />

FIGURE 33.8<br />

INTERBUS cycle times as a function of the number of nodes and the used payload size.<br />

The frame overhead of 6 bytes is caused by a 2 byte long loopback word and a 4 byte long FCS. Each octet<br />

at layer 2 is transmitted within a 13 bit data telegram at layer 1. Depending on the total amount of input<br />

and output data, the total payload size can be calculated by<br />

i= k<br />

i=<br />

k<br />

⎛<br />

Input<br />

n = max ⎜∑PLi<br />

,<br />

∑PLi<br />

⎝<br />

i<br />

where<br />

n is the total payload size: sum of all user data [bytes] of all devices k with n ≤ 512 bytes and k ≤ 512<br />

T Bit is the bit time: 2.μs at 0.5.Mbps or 0.5.μs at 2.Mbps<br />

T SW is the software runtime of the master (depending on implementation)<br />

PL i is the layer 2 payload size of the ith device [bytes] where 1 ≤ i ≤ k and k ≤ 512<br />

In Figure 33.8, the INTERBUS cycle time at the MAC level with a bit rate of 2 Mbps and a software runtime<br />

of 0.7.ms is illustrated as a function of the number of nodes k and their corresponding payload size PL.<br />

33.5 Summary<br />

INTERBUS is a serial bus system developed for the time-critical data transfer at the field level of <strong>industrial</strong><br />

automation <strong>systems</strong>. The physical topology of INTERBUS is based on a ring structure, that is, all devices are<br />

actively integrated in a closed transmission path. The data forward and return lines in the INTERBUS system<br />

are led to all devices via a single cable. This means that the general physical appearance of the system is an<br />

“open” tree structure. Due to a total frame approach, the cyclic data transfer of INTERBUS is very efficient<br />

in comparison to fieldbus <strong>systems</strong> based on an individual frame approach. As a result, small cycle times can<br />

be achieved with small bit rates. Acyclic messages are transmitted using preconfigured time slots within the<br />

total frame in conjunction with a segmentation and recombination mechanism at layer 2.<br />

References<br />

1. IEC, Digital data <strong>communication</strong> for measurement and control—Fieldbus for use in <strong>industrial</strong><br />

control <strong>systems</strong>, 2001, IEC 61158 Ed.3, Type 8 (INTERBUS), IEC, Geneva.<br />

2. INTERBUS Club, www.interbusclub.com, visited May 2009.<br />

3. Baginski, A. and Müller, M., INTERBUS Basics and Practice, Hüthig-Verlag, Heidelberg, Germany,<br />

2002 (German).<br />

i<br />

Output<br />

⎞<br />

⎟<br />

⎠<br />

© <strong>2011</strong> by Taylor and Francis Group, LLC

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