wilamowski-b-m-irwin-j-d-industrial-communication-systems-2011

INTERBUS 33-3
One total frame
Loopback Field 1 Field 2 Field 3 Field 4
Field n FCS Control
PLC
Station 1 Station 2 Station 3 Station 4 Station n
FIGURE 33.2
The layer 2 summation frame structure of INTERBUS.
The layer 2 summation frame consists of a special 16 bit loopback word (i.e., the preamble), the user
data of all devices, and a terminating 32 bit frame check sequence (FCS) to control the data integrity.
The FCS consists of a 16 bit cyclical redundancy check (CRC) value and further 16 bits for controlling
the data exchange between the input and output registers. According to the physical structure, data can
be sent and received by the ring structure of the INTERBUS system in a single round (full duplex mode),
and this results in very high protocol efficiency.
The logical method of operation of an INTERBUS slave can be configured between its incoming and
outgoing interfaces by the register set shown in Figure 33.3. Each INTERBUS slave is part of a large,
distributed SR ring, whose start and end point is the INTERBUS master. The register set inside the slave
can be used for both data transfer and management. Data transfer is performed through the input and
output data registers.
During the data transfer phase, the input data register will contain input data, that is, data that are to
be transmitted to the master, and the output data registers will contain data received through the ring.
CRCregister
CRCregister
Input data register
Identification data register
Selector
Incoming
data flow
Control data register
Output data register
Outgoing
data flow
FIGURE 33.3
Basic model of an INTERBUS slave node.
© 2011 by Taylor and Francis Group, LLC