wilamowski-b-m-irwin-j-d-industrial-communication-systems-2011

33-4 Industrial Communication Systems
Out data
Out data
N N – 1
Loopback
word
1
2
Input
buffer
N
1
2
Output
buffer
N
Loopback
word
In data
Out data
Data flow
inside the
shift registers
In data
Out data
1
2
Master
In data
In data
FIGURE 33.4
Logical structure of the ring in INTERBUS.
According to the logical structure shown in Figure 33.4, the summation frame will shift inside all the
SRs and this way data sent by the master will cross all the nodes. There is a precise time instant when
all output data registers inside each slave will contain the data addressed to that slave. At that moment,
data contained in the output data register will be stored into the node, whereas data addressed to the
master will be loaded into the input data register and will begin to travel along the ring by substituting
the original data into the summation frame. This operating mode is very efficient allowing the ring, into
a single round, to transfer data from and to the master.
An important role is played by the CRC register, which is switched to the input data register in
parallel. The Comité Consultatif International Téléphonique et Télégraphique (CCITT) polynomial
g(x) = x 16 + x 12 + x 5 + 1 is used for the CRC, which is able to detect burst errors shorter than 16 bits. The
CRC registers are used during the frame check sequence to check whether the data have been transmitted
correctly. An important point is that, since the CRC is located at the end of the summation frame, each
slave checks the data correctness only when the whole frame has crossed inside it, but as data contained
into the summation frame are changed during the crossing of the various slaves, CRC must be recalculated
several times. For this reason, two CRC registers are present into each node. The first one (on the left side
Figure 33.3) is used to check incoming data, whereas the second one (on the right side Figure 33.3) is used
to calculate the new CRC value to be attached at the end of the summation frame.
The length of the I/O data registers in each node depends on the number of I/Os of the individual
node. The master needs to know which and how many devices are connected to the bus so that it can
assign the right I/O data to the right device. For this reason, once the bus system has been switched
on, the master starts a series of identification cycles, which enable it to detect how many and which
devices are connected. Each slave has an identification data register with a fixed length 16 bit identification
code.
The master can use this identification code to assign a slave node to a defined device class (e.g., digital
I/O node and analog I/O node) and detect the length of the I/O data registers in a data cycle. The control
data registers are switched in parallel to the identification data registers, whereby the individual devices
can be managed by the master. Commands are transmitted, for example, for local resets or outgoing
© 2011 by Taylor and Francis Group, LLC