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41-2 Industrial Communication Systems<br />

To external memory<br />

MAC<br />

processor<br />

Network<br />

processor<br />

Appl.<br />

processor<br />

ROM<br />

EEPROM<br />

RAM<br />

Address bus (16 bit)<br />

Data bus (8 bit)<br />

Control<br />

Timer/<br />

counter<br />

Application I/O<br />

Network<br />

Com. Port<br />

Reset Service<br />

Clock<br />

IO 0 ... 10<br />

To application specific HW<br />

CP 0 ... 4<br />

To transceiver<br />

FIGURE 41.1<br />

Structure of a Neuron Chip.<br />

As shown in Figure 41.1, the Neuron Chip implements a three-processor architecture with shared<br />

memory, which includes the firmware ROM, an EEPROM for the user application program, and RAM.<br />

Each of the three processors handles a certain task:<br />

The media access control (MAC) processor sends and receives messages to and from the <strong>communication</strong><br />

medium with support of the transceiver, which handles the line coding for a specific medium.<br />

Since many different transceiver types exist, a wide range of <strong>communication</strong> media can be used, such<br />

as twisted pair, power line, fiber optics, and radio frequency. The network processor handles the upper<br />

layers of the LonTalk protocol, which are described in the next section. And the application processor<br />

runs the user application implementing the specific task of the node.<br />

The <strong>communication</strong> among the three processors is realized in shared RAM by <strong>communication</strong> buffers<br />

and flags. There are input and output buffer queues storing messages to be forwarded to the other<br />

processors. Special flag bytes indicate that the other processor should do a certain action, such as creating,<br />

sending, or receiving a message.<br />

Peripheral hardware, such as sensors and actuators, are connected to a set of I/O pins, which can be<br />

configured in a range of single bit input and output for switches or LEDs via nibble and byte input and<br />

output up to higher I/O protocols, such as serial and parallel interfaces, I 2 C, and Magcard.<br />

There are also alternatives to the Neuron Chip. For example, LOYTEC offers a more powerful ARM7-<br />

based embedded controller (LC3020) that implements the LonTalk protocol according to CEA-709 as<br />

well. It also supports LonWorks/IP (standardized as CEA-852 [8]), where LonTalk messages are tunneled<br />

over LAN or Internet in IP packets. Such controllers are used for more complex tasks, like panels<br />

with a graphical user interface or IP routers.<br />

To identify the LonWorks nodes in the network, each Neuron Chip has a fixed 48 bit identifier called<br />

Neuron ID assigned by the manufacturer. A LonWorks node can actively transmit its Neuron ID in a<br />

service pin message, when a special service pin is pressed on the node. This simplifies the network integration,<br />

when new nodes have to be added to the network, because it is not required to enter the Neuron<br />

ID manually in the management tool. Instead, the management tool simply has to wait for the service<br />

pin message.<br />

During configuration, a logical address is assigned to each node. It consists of the domain, subnet,<br />

and node ID. The domain represents a whole LonWorks network, which is identified by the domain ID<br />

with up to 6 bytes length. Direct message passing among domains is not possible, but it can be done via<br />

gateways.<br />

© <strong>2011</strong> by Taylor and Francis Group, LLC

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