wilamowski-b-m-irwin-j-d-industrial-communication-systems-2011

Embedded Networks in Civilian Aircraft Avionics Systems 24-11
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FIGURE 24.9
AFDX VLs shaping and policing.
100.Mbps capacity. Moreover, the network integrator is responsible for VL placement: A multipath
VL (a tree originating from the emitter) has to be statically allocated on the network’s physical topology
and the path can be chosen from among several possibilities.
One must note that guaranteeing bandwidth on the network requires that all VLs remain compliant
with their specified BAG and S max parameters; otherwise, the sum of some VL bandwidths could possibly
exceed the 100.Mbps capacity. For this reason, every VL is shaped inside the emitter end system, and
all incoming VLs are also controlled by policers at the switch level; frames exceeding the VL’s contract
are deleted by the switches (leaky bucket algorithm) as represented in Figure 24.9.
24.6.4.2 VL Latency Guarantee
The communication latency of an ARINC 429 data bus is very easy to measure. It is simply the time
required to emit data plus a negligible propagation time; it is absolutely deterministic.
The picture is completely different for a VL on an AFDX network. Obviously, the latency of a frame
cannot be predicted as it depends on whether or not the frame will be delayed by other frames sharing a
section of its path. Thus, a strong form of determinism cannot be obtained; a weaker form of determinism
is proposed, it is based on VL end-to-end latency upper bounding methods. VLs competing for a
given switch output port generate contentions in the output port queue and can be delayed depending
on the number of confluent VLs and their characteristics (maximum frame size for example).
Of course, end-to-end latencies have to be compared to the real-time constraints of avionics communications,
but in reality, these constraints are very different from one avionics function to another. Thus,
in the early prototype specifications, a maximum latency of 1.ms per switch crossing was integrated into
the switch specification. When four or five switches are crossed, the maximum obtained latency is comparable
with the highest “freshness” required for some critical data. At 100.Mbps, 1.ms of continuous
emission of minimum-sized frames represents nearly 150 frames exiting from an output port’s queue.
Of course, the physical size of the switches’ queues is the actual constraint: overflowing this queue
capacity necessarily implies lost frames.
24.6.4.3 VL Jitter Issues
Jitter is the third parameter of a VL, after the BAG and S max . As the AFDX definition in the ARINC
664 standard states, jitter is considered null at the output of the end system shapers applied to each
VL. Since the VLs are multiplexed in the end system just after having been shaped, as represented
in Figure 24.10, jitter is non-null at the output of the multiplexer and is limited by two bounds: the
first one comes from the calculation of the multiplexer’s latency and the second is an absolute value
of 500.μs.
This value has been chosen as half the minimal BAG in order to avoid burst occurrences where a
frame pertaining to some VLs would be overtaken by a following frame of the same VL. Of course,
avoiding this problem in end systems does not prevent it from occurring later down the network.
© 2011 by Taylor and Francis Group, LLC