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LIN-Bus 45-5<br />

Reverse battery protection<br />

diode (D1)<br />

V Shift_BAT<br />

Transceiver IC<br />

D ser_int<br />

D ser_Master<br />

SCI<br />

Rx<br />

V SUP<br />

R<br />

LIN<br />

V BAT<br />

LIN node<br />

Only within<br />

V BATTERY V SUP<br />

a master node<br />

30 K 1 K<br />

Rx<br />

V (LIN)<br />

Bus<br />

Tx<br />

GND<br />

V Shift_GND<br />

Tx<br />

Voltage divider<br />

(a)<br />

GND<br />

(b)<br />

FIGURE 45.5<br />

(a) Basic principle of the physical layer according to ISO 9141. (b) Basic structure of a LIN master node.<br />

is mandatory to prevent uncontrolled powering of the node from the bus line, in the case of a battery<br />

loss, that is, if V BAT is disconnected in Figure 45.5b. The pull-up resistor is specified at 30.kΩ on a slave<br />

node and at 1.kΩ on a master node. The baud rate is specified in the range of 1–20.kbps but typical baud<br />

rates are 9.6 or 19.2.kbps, or 10.4.kbps according to SAE J2602, as will be discussed later.<br />

45.4.1 Signal Specification<br />

The V SUP and GND form the reference potential of the voltage divider to determine the logical value of a bit.<br />

A voltage level below 40% V SUP represents logical 0 and a level above 60% V SUP represents a logical 1. The<br />

transmitter has to ensure that the receiver receives valid voltage levels. The specification does not define<br />

transmitter voltage levels.<br />

Because any node determines the logical bit values in reference to its own V SUB and GND, a drift has<br />

an impact on this process (see Figure 45.6). The specification margins the drift of V BAT (V Shift_BAT ) and<br />

GND (V Shift_GND ) at about 10%. Note that V SUP , seen in Figure 45.5b, can be computed as<br />

LIN signal<br />

VSUP = VBAT − VD1<br />

(45.1)<br />

Rx—50% duty<br />

cycle<br />

Rx—min. duty<br />

cycle<br />

Rx—max. duty<br />

cycle<br />

FIGURE 45.6<br />

Influence of the drift.<br />

© <strong>2011</strong> by Taylor and Francis Group, LLC

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