Intel® 64 and IA-32 Architectures Optimization Reference Manual

GENERAL OPTIMIZATION GUIDELINESUsing LEA in this way may avoid register usage by not tying up registers for operandsof arithmetic instructions. This use may also save code space.If the LEA instruction uses a shift by a constant amount then the latency of thesequence of µops is shorter if adds are used instead of a shift, and the LEA instructionmay be replaced with an appropriate sequence of µops. This, however, increases thetotal number of µops, leading to a trade-off.Assembly/Compiler Coding Rule 33. (ML impact, L generality) If an LEAinstruction using the scaled index is on the critical path, a sequence with ADDs maybe better. If code density and bandwidth out of the trace cache are the criticalfactor, then use the LEA instruction.3.5.1.4 Using SHIFT and ROTATEThe SHIFT and ROTATE instructions have a longer latency on processor with a CPUIDsignature corresponding to family 15 and model encoding of 0, 1, or 2. The latency ofa sequence of adds will be shorter for left shifts of three or less. Fixed and variableSHIFTs have the same latency.The rotate by immediate and rotate by register instructions are more expensive thana shift. The rotate by 1 instruction has the same latency as a shift.Assembly/Compiler Coding Rule 34. (ML impact, L generality) Avoid ROTATEby register or ROTATE by immediate instructions. If possible, replace with aROTATE by 1 instruction.3.5.1.5 Address CalculationsFor computing addresses, use the addressing modes rather than general-purposecomputations. Internally, memory reference instructions can have four operands:• Relocatable load-time constant• Immediate constant• Base register• Scaled index registerIn the segmented model, a segment register may constitute an additional operand inthe linear address calculation. In many cases, several integer instructions can beeliminated by fully using the operands of memory references.3.5.1.6 Clearing Registers and Dependency Breaking IdiomsCode sequences that modifies partial register can experience some delay in itsdependency chain, but can be avoided by using dependency breaking idioms.In processors based on Intel Core microarchitecture, a number of instructions canhelp clear execution dependency when software uses these instruction to clearregister content to zero. The instructions include3-27