Intel® 64 and IA-32 Architectures Optimization Reference Manual

INSTRUCTION LATENCY AND THROUGHPUTof processors based on Intel NetBurst microarchitecture ranges from 0, 1, 2, 3, 4,and 6. The data shown for 0F_03H also applies to OF_04H, and 0F_06H.Pentium M processor instruction timing data is shown in the columns represented by“DisplayFamilyValue_DisplayModelValue” of 06_09H, and 06_0DH.Intel Core Solo and Intel Core Duo processors are represented by 06_0EH. Processorsbases on Intel Core microarchitecture are represented by 06_0FH.Table C-1. Supplemental Streaming SIMD Extension 3 SIMD InstructionsInstruction Latency 1 ThroughputDisplayFamily_DisplayModel 06_0FH 06_0FHPALIGNR mm1, mm2, imm 2 1PALIGNR xmm1, xmm2, imm 2 1PHADDD mm1, mm2 3 2PHADDD xmm1, xmm2 5 3PHADDW/PHADDSW mm1, mm2 5 4PHADDW/PHADDSW xmm1, xmm2 6 4PHSUBD mm1, mm2 3 2PHSUBD xmm1, xmm2 5 3PHSUBW/PHSUBSW mm1, mm2 5 4PHSUBW/PHSUBSW xmm1, xmm2 6 4PMADDUBSW mm1, mm2 3 1PMADDUBSW xmm1, xmm2 3 1PMULHRSW mm1, mm2 3 1PMULHRSW xmm1, xmm2 3 1PSHUFB mm1, mm2 1 1PSHUFB xmm1, xmm2 3 2PSIGNB/PSIGND/PSIGNW mm1, mm2 1 0.5PSIGNB/PSIGND/PSIGNW xmm1, xmm2 1 0.5See Appendix C.3.2, “Table Footnotes”C-4