IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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USING PERFORMANCE MONITORING EVENTSMetricSSE Input AssistsPacked SP Retired 1Packed DP Retired 1Scalar SP Retired 1Scalar DP Retired 164-bit MMXInstructions Retired 1128-bit MMXInstructions Retired 1X87 Retired 2Stalled Cycles of StoreBuffer Resources (nonstandard3 )Table B-6. Performance Metrics - Characterization (Contd.)DescriptionNumber ofoccurrences ofSSE/SSE2 floatingpointoperationsneeding assistance tohandle an exceptionconditionThe number ofoccurrences includesspeculative counts.Non-bogus packedsingle-precisioninstructions retiredNon-bogus packeddouble-precisioninstructions retiredNon-bogus scalarsingle-precisioninstructions retiredNon-bogus scalardouble-precisioninstructions retiredNon-bogus 64-bitinteger SIMDinstruction (MMXinstructions) retiredNon-bogus 128-bitinteger SIMDinstructions retiredNon-bogus x87floating-pointinstructions retiredDuration of stalls dueto lack of store buffersEvent Name or MetricExpressionSSE_input_assistExecution_event; setthis execution tag:Packed_SP_retiredExecution_event; setthis execution tag:Packed_DP_retiredExecution_event; setthis execution tag:Scalar_SP_retiredExecution_event; setthis execution tag:Scalar_DP_retiredExecution_event; setthe followingexecution tag:64_bit_MMX_retiredExecution_event; setthis execution tag:128_bit_MMX_retiredExecution_event; setthis execution tag:X87_FP_retiredResource_stallEvent Mask ValueRequiredALLNONBOGUS0NONBOGUS0NONBOGUS0NONBOGUS0NONBOGUS0NONBOGUS0NONBOGUS0SBFULLB-28
USING PERFORMANCE MONITORING EVENTSMetricStalls of Store BufferResources (nonstandard3 )Table B-6. Performance Metrics - Characterization (Contd.)DescriptionNumber of allocationstalls due to lack ofstore buffersEvent Name or MetricExpressionResource_stallEvent Mask ValueRequiredSBFULL(Also set the followingCCCR bits: Compare=1;Edge=1;Threshold=0)NOTES:1. Most MMX technology instructions, Streaming SIMD Extensions and Streaming SIMD Extensions 2decode into a single mop. There are some instructions that decode into several mops; in these limitedcases, the metrics count the number of mops that are actually tagged.2. Most commonly used x87 instructions (e.g., fmul, fadd, fdiv, fsqrt, fstp, etc.) decode into a singlemop.However, transcendental and some x87 instructions decode into several mops; in these limitedcases, the metrics will count the number of mops that are actually tagged.3. This metric may not be supported in all models of the Pentium 4 processor family.Table B-7. Performance Metrics - Machine ClearMetric Description Event Name or MetricExpressionMachine Clear Count Number of cycles that Machine_clearentire pipeline of themachine is cleared forall causesMemory OrderMachine ClearSelf-modifying CodeClearNumber of timesentire pipeline of themachine is cleared dueto memory-orderingissuesNumber of timesentire pipeline of themachine is cleared dueto self-modifying codeissuesMachine_clearMachine_clearEvent Mask ValueRequiredCLEAR(Also set the followingCCCR bits: Compare=1;Edge=1; Threshold=0)MOCLEARSMCCLEARB-29
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESpred
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GENERAL OPTIMIZATION GUIDELINESIn t
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESmiss
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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OPTIMIZING CACHE USAGE• If a proc
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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Page 346 and 347: POWER OPTIMIZATION FOR MOBILE USAGE
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Page 370 and 371: USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTT
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSto
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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Intel Corp.999 CANADA PLACE,Suite 4
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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