IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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OPTIMIZING FOR SIMD INTEGER APPLICATIONSTable 5-1. PAHUF EncodingBitsWords1 - 0 03 - 2 15 - 4 27 - 6 3Bits 7 and 6 encode for word 3 in MMX register ([63-48]). Similarly, the 2-bitencoding represents which source word is used, for example, binary encoding of 10indicates that source word 2 in MMX register/memory (MM/MEM[47-32]) is used.See Figure 5-8 and Example 5-13.63MM/m64X4 X3 X2 X1063MMX1 X2 X3 X40OM15166Figure 5-8. pshuf PSHUF InstructionExample 5-13. PSHUF Instruction Code; Input:; edi source value; Output:; MM1 MM register containing re-arranged wordsmovq mm0, [edi]pshufw mm1, mm0, 0x1b5-16
OPTIMIZING FOR SIMD INTEGER APPLICATIONS5.4.10 Packed Shuffle Word for 128-bit RegistersThe PSHUFLW/PSHUFHW instruction performs a full shuffle of any source word fieldwithin the low/high 64 bits to any result word field in the low/high 64 bits, using an8-bit immediate operand; other high/low 64 bits are passed through from the sourceoperand.PSHUFD performs a full shuffle of any double-word field within the 128-bit source toany double-word field in the 128-bit result, using an 8-bit immediate operand.No more than 3 instructions, using PSHUFLW/PSHUFHW/PSHUFD, are required toimplement many common data shuffling operations. Broadcast, Swap, and Reverseare illustrated in Example 5-14, Example 5-15, and Example 5-16.Example 5-14. Broadcast Code, Using 2 Instructions/* Goal: Broadcast the value from word 5 to all words *//* Instruction Result */| 7| 6| 5| 4| 3| 2| 1| 0|PSHUFHW (3,2,1,1)| 7| 6| 5| 5| 3| 2| 1| 0|PSHUFD (2,2,2,2) | 5| 5| 5| 5| 5| 5| 5| 5|Example 5-15. Swap Code, Using 3 Instructions/* Goal: Swap the values in word 6 and word 1 *//* Instruction Result */| 7| 6| 5| 4| 3| 2| 1| 0|PSHUFD (3,0,1,2) | 7| 6| 1| 0| 3| 2| 5| 4|PSHUFHW (3,1,2,0)| 7| 1| 6| 0| 3| 2| 5| 4|PSHUFD (3,0,1,2) | 7| 1| 5| 4| 3| 2| 6| 0|5-17
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESpred
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINES—
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Page 172 and 173: CODING FOR SIMD ARCHITECTURESmance
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Page 182 and 183: CODING FOR SIMD ARCHITECTURES• Us
Page 184 and 185: CODING FOR SIMD ARCHITECTURESpatter
Page 186 and 187: CODING FOR SIMD ARCHITECTURESmoves
Page 188 and 189: CODING FOR SIMD ARCHITECTURES4-28
Page 190 and 191: OPTIMIZING FOR SIMD INTEGER APPLICA
Page 228 and 229: OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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OPTIMIZING CACHE USAGE• If a proc
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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APPLICATION PERFORMANCE TOOLSThe /f
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APPLICATION PERFORMANCE TOOLSTable
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APPLICATION PERFORMANCE TOOLSA.1.6.
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSprogra
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APPLICATION PERFORMANCE TOOLSThe Li
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APPLICATION PERFORMANCE TOOLSA.5 IN
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USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUTo
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INSTRUCTION LATENCY AND THROUGHPUTT
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSto
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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