IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURESA+2, the DPL prefetches cache line A+3. The DPL works similarly for “downward”loops.The Intel Pentium M processor introduced DPL. The Intel Core microarchitectureadded the following features to DPL:• The DPL can detect more complicated streams, such as when the stream skipscache lines. DPL may issue 2 prefetch requests on every L2 lookup. The DPL inthe Intel Core microarchitecture can run up to 8 lines ahead from the loadrequest.• DPL in the Intel Core microarchitecture adjusts dynamically to bus bandwidth andthe number of requests. DPL prefetches far ahead if the bus is not busy, and lessfar ahead if the bus is busy.• DPL adjusts to various applications and system configurations.Entries for the two cores are handled separately.2.1.4.4 Store ForwardingIf a load follows a store and reloads the data that the store writes to memory, theIntel Core microarchitecture can forward the data directly from the store to the load.This process, called store to load forwarding, saves cycles by enabling the load toobtain the data directly from the store operation instead of through memory.The following rules must be met for store to load forwarding to occur:• The store must be the last store to that address prior to the load.• The store must be equal or greater in size than the size of data being loaded.• The load cannot cross a cache line boundary.• The load cannot cross an 8-Byte boundary. 16-Byte loads are an exception to thisrule.• The load must be aligned to the start of the store address, except for thefollowing exceptions:— An aligned 64-bit store may forward either of its 32-bit halves— An aligned 128-bit store may forward any of its 32-bit quarters— An aligned 128-bit store may forward either of its 64-bit halvesSoftware can use the exceptions to the last rule to move complex structures withoutlosing the ability to forward the subfields.2.1.4.5 Memory DisambiguationA load instruction μop may depend on a preceding store. Many microarchitecturesblock loads until all preceding store address are known.2-16
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURESThe memory disambiguator predicts which loads will not depend on any previousstores. When the disambiguator predicts that a load does not have such a dependency,the load takes its data from the L1 data cache.Eventually, the prediction is verified. If an actual conflict is detected, the load and allsucceeding instructions are re-executed.2.1.5 Intel ® Advanced Smart CacheThe Intel Core microarchitecture optimized a number of features for two processorcores on a single die. The two cores share a second-level cache and a bus interfaceunit, collectively known as Intel Advanced Smart Cache. This section describes thecomponents of Intel Advanced Smart Cache. Figure 2-3 illustrates the architecture ofthe Intel Advanced Smart Cache.Core 1BranchPredictionCore 0BranchPredictionRetirementExecutionFetch/DecodeRetirementExecutionFetch/DecodeL1 DataCacheL1 Instr.CacheL1 DataCacheL1 Instr.CacheL2 CacheBus Interface UnitSystem BusFigure 2-3. Intel Advanced Smart Cache ArchitectureTable 2-3 details the parameters of caches in the Intel Core microarchitecture. Forinformation on enumerating the cache hierarchy identification using the deterministiccache parameter leaf of CPUID instruction, see the Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volume 2A.2-17
Page 1 and 2: NIntel® 64 and IA-32 Architectures
Page 4 and 5: CONTENTS2.3.1 Front End. . . . . .
Page 6 and 7: CONTENTS3.7 PREFETCHING . . . . . .
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Page 10 and 11: CONTENTS9.5.3 Streaming Store Instr
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Page 15 and 16: CONTENTSExample 4-1. Identification
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Page 19 and 20: CONTENTSFigure 9-7. Cache Blocking
Page 21 and 22: CHAPTER 1INTRODUCTIONThe Intel® 64
Page 23 and 24: INTRODUCTION• Chapter 10: Power O
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEExample 9-11.
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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APPLICATION PERFORMANCE TOOLSThe /f
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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