Intel® 64 and IA-32 Architectures Optimization Reference Manual

GENERAL OPTIMIZATION GUIDELINESrequest bandwidth and delivers significantly lower data bandwidth. This difference isdepicted in Examples 3-39 and 3-40.Example 3-39. Using Non-temporal Stores and 64-byte Bus Write Transactions#define STRIDESIZE 256lea ecx, p64byte_Alignedmov edx, ARRAY_LENxor eax, eaxslloop:movntps XMMWORD ptr [ecx + eax], xmm0movntps XMMWORD ptr [ecx + eax+16], xmm0movntps XMMWORD ptr [ecx + eax+32], xmm0movntps XMMWORD ptr [ecx + eax+48], xmm0; 64 bytes is written in one bus transactionadd eax, STRIDESIZEcmp eax, edxjl slloopExample 3-40. On-temporal Stores and Partial Bus Write Transactions#define STRIDESIZE 256Lea ecx, p64byte_AlignedMov edx, ARRAY_LENXor eax, eaxslloop:movntps XMMWORD ptr [ecx + eax], xmm0movntps XMMWORD ptr [ecx + eax+16], xmm0movntps XMMWORD ptr [ecx + eax+32], xmm0; Storing 48 bytes results in 6 bus partial transactionsadd eax, STRIDESIZEcmp eax, edx3.7 PREFETCHINGRecent Intel processor families employ several prefetching mechanisms to acceleratethe movement of data or code and improve performance:• Hardware instruction prefetcher• Software prefetch for data• Hardware prefetch for cache lines of data or instructions3-68