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Intel® 64 and IA-32 Architectures Optimization Reference Manual

Intel® 64 and IA-32 Architectures Optimization Reference Manual

Intel® 64 and IA-32 Architectures Optimization Reference Manual

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INTEL® <strong>64</strong> AND <strong>IA</strong>-<strong>32</strong> PROCESSOR ARCHITECTURES• Instructions that reference <strong>32</strong>-bit general purpose registers can access 16general purpose registers in <strong>64</strong>-bit mode.<strong>64</strong>-bit MMX RegistersMM7MM6MM5MM4MM3MM2MM1MM0128-bit XMM RegistersXMM7XMM6XMM5XMM4XMM3XMM2XMM1XMM0OM15149Figure 2-10. SIMD Instruction Register UsageSIMD improves the performance of 3D graphics, speech recognition, imageprocessing, scientific applications <strong>and</strong> applications that have the following characteristics:• inherently parallel• recurring memory access patterns• localized recurring operations performed on the data• data-independent control flowSIMD floating-point instructions fully support the IEEE St<strong>and</strong>ard 754 for BinaryFloating-Point Arithmetic. They are accessible from all <strong>IA</strong>-<strong>32</strong> execution modes:protected mode, real address mode, <strong>and</strong> Virtual 8086 mode.SSE, SSE2, <strong>and</strong> MMX technologies are architectural extensions. Existing software willcontinue to run correctly, without modification on Intel microprocessors that incorporatethese technologies. Existing software will also run correctly in the presence ofapplications that incorporate SIMD technologies.SSE <strong>and</strong> SSE2 instructions also introduced cacheability <strong>and</strong> memory orderinginstructions that can improve cache usage <strong>and</strong> application performance.2-47

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