Intel® 64 and IA-32 Architectures Optimization Reference Manual

OPTIMIZING FOR SIMD INTEGER APPLICATIONSConsider a case with a series of small loads after a large store to the same area ofmemory (beginning at memory address MEM), as shown in Example 5-33. Most ofthe small loads stall because they are not aligned with the store. See Section 3.6.4,“Store Forwarding,” for details.Example 5-33. A Series of Small Loads After a Large Storemovq mem, mm0 ; store qword to address “mem"::mov bx, mem + 2 ; load word at “mem + 2" stallsmov cx, mem + 4 ; load word at “mem + 4" stallsThe word loads must wait for the quadword store to write to memory before they canaccess the data they require. This stall can also occur with other data types (forexample: when doublewords or words are stored and then words or bytes are readfrom the same area of memory).When you change the code sequence as shown in Example 5-34, the processor canaccess the data without delay.Example 5-34. Eliminating Delay for a Series of Small Loads after a Large Storemovq mem, mm0 ; store qword to address “mem"::movq mm1, mem ; load qword at address “mem"movd eax, mm1 ; transfer “mem + 2" to eax from; MMX register, not memorypsrlq mm1, 32shr eax, 16movd ebx, mm1 ; transfer “mem + 4" to bx from; MMX register, not memoryand ebx, 0ffffhThese transformations, in general, increase the number of instructions required toperform the desired operation. For Pentium II, Pentium III, and Pentium 4 processors,the benefit of avoiding forwarding problems outweighs the performance penalty dueto the increased number of instructions.5-33