Intel® 64 and IA-32 Architectures Optimization Reference Manual

MULTICORE AND HYPER-THREADING TECHNOLOGYExample 8-4. Spin-wait Loop and PAUSE Instructions(a) An un-optimized spin-wait loop experiences performance penalty when exiting the loop. Itconsumes execution resources without contributing computational work.do {// This loop can run faster than the speed of memory access,// other worker threads cannot finish modifying sync_var until// outstanding loads from the spinning loops are resolved.} while( sync_var != constant_value);(b) Inserting the PAUSE instruction in a fast spin-wait loop prevents performance-penalty to thespinning thread and the worker threaddo {_asm pause// Ensure this loop is de-pipelined, i.e. preventing more than one// load request to sync_var to be outstanding,// avoiding performance penalty when the worker thread updates// sync_var and the spinning thread exiting the loop.}while( sync_var != constant_value);(c) A spin-wait loop using a “test, test-and-set” technique to determine the availability of thesynchronization variable. This technique is recommended when writing spin-wait loops to run onIntel 64 and IA-32 architecture processors.Spin_Lock:CMP lockvar, 0 ;// Check if lock is free.JE Get_lockPAUSE;// Short delay.JMP Spin_Lock;Get_Lock:MOV EAX, 1;XCHG EAX, lockvar; // Try to get lock.CMP EAX, 0; // Test if successful.JNE Spin_Lock;Critical_Section:MOV lockvar, 0; // Release lock.User/Source Coding Rule 20. (M impact, H generality) Insert the PAUSEinstruction in fast spin loops and keep the number of loop repetitions to a minimumto improve overall system performance.On processors that use the Intel NetBurst microarchitecture core, the penalty ofexiting from a spin-wait loop can be avoided by inserting a PAUSE instruction in theloop. In spite of the name, the PAUSE instruction improves performance by introducinga slight delay in the loop and effectively causing the memory read requests to8-17