Intel® 64 and IA-32 Architectures Optimization Reference Manual

INSTRUCTION LATENCY AND THROUGHPUTTable C-10a. General Purpose Instructions (Contd.)Instruction Latency 1 ThroughputDisplayFamily_DisplayModel06_0FH06_0EH06_0DH06_09H06_0FH06_0EH06_0DHCLC/CMC 1 0.33CLI 9 11 11 11 9 11 11 11CMOV 2 0.5CMP/TEST 1 1 1 1 0.5 0.5 0.5 0.5DEC/INC 1 1 1 1 0.33 0.5 0.5 0.5IMUL r32 3 4 4 4 0.5 1 1 1IMUL imm32 3 4 4 4 0.5 1 1 1IDIV 22 22 38 22 22 38MOVSB/MOVSW 1 1 1 1 0.33 0.5 0.5 0.5MOVZB/MOVZW 1 1 1 1 0.33 0.5 0.5 0.5NEG/NOT/NOP 1 1 1 1 0.33 0.5 0.5 0.5PUSH 3 3 3 3 1 1 1 1RCL/RCR 1 1 1 1 1 1ROL/ROR 1 1 1 1 0.33 1 1 1SAHF 1 1 1 1 0.33 0.5 0.5 0.5SAL/SAR/SHL/SHR 1 0.33SETcc 1 1 1 1 0.33 0.5 0.5 0.5XCHG 3 2 2 2 1 1 1 1See Appendix C.3.2, “Table Footnotes”06_09HC.3.2Table FootnotesThe following footnotes refer to all tables in this appendix.1. Latency information for many instructions that are complex (> 4 μops) areestimates based on conservative (worst-case) estimates. Actual performance ofthese instructions by the out-of-order core execution unit can range fromsomewhat faster to significantly faster than the latency data shown in thesetables.2. The names of execution units apply to processor implementations of the IntelNetBurst microarchitecture with a CPUID signature of family 15, model encoding= 0, 1, 2. They include: ALU, FP_EXECUTE, FPMOVE, MEM_LOAD, MEM_STORE.See Figure 2-5 for execution units and ports in the out-of-order core. Note thefollowing:C-25