IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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USING PERFORMANCE MONITORING EVENTSMOB Load Replays2nd Level Cache ReadMisses 22nd Level Cache ReadReferences 23rd Level Cache ReadMisses 23rd Level Cache ReadReferences 22nd Level Cache ReadsHit SharedTable B-4. Performance Metrics - Memory (Contd.)Metric Description Event Name or MetricExpressionNumber of replayedloads related to theMemory Order Buffer(MOB)This metric counts onlythe case where thestore-forwarding datais not an alignedsubset of the storeddata.Number of 2nd-levelcache read misses(load and RFO misses)Beware of granularitydifferences.Number of 2nd levelcache read references(loads and RFOs)Beware of granularitydifferences.Number of 3rd levelcache read misses(load and RFOs misses)Beware of granularitydifferences.Number of 3rd levelcache read references(loads and RFOs)Beware of granularitydifferences.Number of 2nd levelcache read references(loads and RFOs) thathit cache line in sharedstateBeware of granularitydifferences.MOB_load_replayBSQ_cache_referenceBSQ_cache_referenceBSQ_cache_referenceBSQ_cache_referenceBSQ_cache_referenceEvent Mask ValueRequiredPARTIAL_DATA,UNALGN_ADDRRD_2ndL_MISSRD_2ndL_HITS,RD_2ndL_HITE,RD_2ndL_HITM,RD_2ndL_MISSRD_3rdL_MISSRD_3rdL_HITS,RD_3rdL_HITE,RD_3rdL_HITM,RD_3rdL_MISSRD_2ndL_HITSB-14
USING PERFORMANCE MONITORING EVENTS2nd Level Cache ReadsHit Modified2nd Level Cache ReadsHit Exclusive3rd Level Cache ReadsHit Shared3rd-Level Cache ReadsHit Modified3rd-Level Cache ReadsHit ExclusiveMOB Load ReplaysRetiredLoads RetiredTable B-4. Performance Metrics - Memory (Contd.)Metric Description Event Name or MetricExpressionNumber of 2nd levelcache read references(loads and RFOs) thathit cache line inmodified stateBeware of granularitydifferences.Number of 2nd levelcache read references(loads and RFOs) thathit cache line inexclusive stateBeware of granularitydifferences.Number of 3rd levelcache read references(loads and RFOs) thathit cache line in sharedstateBeware of granularitydifferences.Number of 3rd levelcache read references(loads and RFOs) thathit cache line inmodified stateBeware of granularitydifferences.Number of 3rd levelcache read references(loads and RFOs) thathit cache line inexclusive stateBeware of granularitydifferences.Number of retired loadμops that experiencedreplays related to MOBNumber of retired loadoperations that weretagged at front endBSQ_cache_referenceBSQ_cache_referenceBSQ_cache_referenceBSQ_cache_referenceBSQ_cache_referenceReplay_event; set thefollowing replay tag:MOB_load_replay_retiredFront_end_event; setfollowing front endtag: Memory_loadsEvent Mask ValueRequiredRD_2ndL_HITMRD_2ndL_HITERD_3rdL_HITSRD_3rdL_HITMRD_3rdL_HITENBOGUSNBOGUSB-15
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESpred
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GENERAL OPTIMIZATION GUIDELINESIn t
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESmiss
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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Page 370 and 371: USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUTo
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INSTRUCTION LATENCY AND THROUGHPUTT
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSto
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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