IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONSX1 X2 X3 X4XFx Fx Fx Fx+Y1 Y2 Y3 Y4XFy Fy Fy Fy+Z1 Z2 Z3 Z4XFz Fz Fz Fz+W1 W2 W3 W4XFw Fw Fw Fw=R1 R2 R3 R4OM15168Figure 6-3. Dot Product OperationFigure 6-3 shows how one result would be computed for seven instructions if thedata were organized as AoS and using SSE alone: four results would require 28instructions.Example 6-1. Pseudocode for Horizontal (xyz, AoS) Computationmulpsmovapsshufpsaddpsmovapsshufpsaddps; x*x', y*y', z*z'; reg->reg move, since next steps overwrite; get b,a,d,c from a,b,c,d; get a+b,a+b,c+d,c+d; reg->reg move; get c+d,c+d,a+b,a+b from prior addps; get a+b+c+d,a+b+c+d,a+b+c+d,a+b+c+d6-6
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONSNow consider the case when the data is organized as SoA. Example 6-2 demonstrateshow four results are computed for five instructions.Example 6-2. Pseudocode for Vertical (xxxx, yyyy, zzzz, SoA) Computationmulpsmulpsmulpsaddpsaddps; x*x' for all 4 x-components of 4 vertices; y*y' for all 4 y-components of 4 vertices; z*z' for all 4 z-components of 4 vertices; x*x' + y*y'; x*x'+y*y'+z*z'For the most efficient use of the four component-wide registers, reorganizing thedata into the SoA format yields increased throughput and hence much better performancefor the instructions used.As seen from this simple example, vertical computation yielded 100% use of theavailable SIMD registers and produced four results. (The results may vary based onthe application.) If the data structures must be in a format that is not “friendly” tovertical computation, it can be rearranged “on the fly” to achieve full utilization of theSIMD registers. This operation is referred to as “swizzling” operation and the reverseoperation is referred to as “deswizzling.”6.5.1.2 Data SwizzlingSwizzling data from one format to another may be required in many algorithms whenthe available instruction set extension is limited (for example: only SSE is available).An example of this is AoS format, where the vertices come as XYZ adjacent coordinates.Rearranging them into SoA format (XXXX, YYYY, ZZZZ) allows more efficientSIMD computations.For efficient data shuffling and swizzling use the following instructions:• MOVLPS, MOVHPS load/store and move data on half sections of the registers.• SHUFPS, UNPACKHPS, and UNPACKLPS unpack data.To gather data from four different memory locations on the fly, follow these steps:1. Identify the first half of the 128-bit memory location.2. Group the different halves together using MOVLPS and MOVHPS to form an XYXYlayout in two registers.3. From the 4 attached halves, get XXXX by using one shuffle, YYYY by usinganother shuffle.ZZZZ is derived the same way but only requires one shuffle. Example 6-3 illustratesthe swizzle function.6-7
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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OPTIMIZING CACHE USAGE• If a proc
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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APPLICATION PERFORMANCE TOOLSThe /f
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APPLICATION PERFORMANCE TOOLSTable
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APPLICATION PERFORMANCE TOOLSA.1.6.
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSprogra
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APPLICATION PERFORMANCE TOOLSThe Li
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APPLICATION PERFORMANCE TOOLSA.5 IN
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USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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