Intel® 64 and IA-32 Architectures Optimization Reference Manual

GENERAL OPTIMIZATION GUIDELINESprefetch to fetch additional cache lines that won’t be needed. If significant negativeperformance impact is detected due to DCU hardware prefetch on a portion of thecode, software can try to reduce the size of that contemporaneous working set to beless than half of the L2 cache.Example 3-42. Avoid Causing DCU Hardware Prefetch to Fetch Un-needed Lineswhile ( CurrBond != NULL ){MyATOM *a1 = CurrBond->At1 ;MyATOM *a2 = CurrBond->At2 ;if ( a1->CurrStep LastStep &&a2->CurrStep LastStep){a1->CurrStep++ ;a2->CurrStep++ ;double ux = a1->Pts[0].x - a2->Pts[0].x ;double uy = a1->Pts[0].y - a2->Pts[0].y ;double uz = a1->Pts[0].z - a2->Pts[0].z ;a1->AuxPts[0].x += ux ;a1->AuxPts[0].y += uy ;a1->AuxPts[0].z += uz ;a2->AuxPts[0].x += ux ;a2->AuxPts[0].y += uy ;a2->AuxPts[0].z += uz ;} ;CurrBond = CurrBond->Next ;} ;To fully benefit from these prefetchers, organize and access the data using one of thefollowing methods:Method 1:• Organize the data so consecutive accesses can usually be found in the same4-KByte page.• Access the data in constant strides forward or backward IP Prefetcher.3-72