Intel® 64 and IA-32 Architectures Optimization Reference Manual

INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURESsame operation being performed on each corresponding pair of data elements (X1and Y1, X2 and Y2, X3 and Y3, and X4 and Y4). The results of the four parallel computationsare sorted as a set of four packed data elements.X4 X3 X2 X1Y4 Y3 Y2 Y1OP OP OP OPX4 op Y4 X3 op Y3 X2 op Y2 X1 op Y1OM15148Figure 2-9. Typical SIMD OperationsThe Pentium 4 processor further extended the SIMD computation model with theintroduction of Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3(SSE3), and Intel Xeon processor 5100 series introduced Supplemental StreamingSIMD Extensions 3 (SSSE3).SSE2 works with operands in either memory or in the XMM registers. The technologyextends SIMD computations to process packed double-precision floating-point dataelements and 128-bit packed integers. There are 144 instructions in SSE2 thatoperate on two packed double-precision floating-point data elements or on 16packed byte, 8 packed word, 4 doubleword, and 2 quadword integers.SSE3 enhances x87, SSE and SSE2 by providing 13 instructions that can accelerateapplication performance in specific areas. These include video processing, complexarithmetics, and thread synchronization. SSE3 complements SSE and SSE2 withinstructions that process SIMD data asymmetrically, facilitate horizontal computation,and help avoid loading cache line splits. See Figure 2-10.SSSE3 provides additional enhancement for SIMD computation with 32 instructionson digital video and signal processing.The SIMD extensions operates the same way in Intel 64 architecture as in IA-32architecture, with the following enhancements:• 128-bit SIMD instructions referencing XMM register can access 16 XMM registersin 64-bit mode.2-46