Intel® 64 and IA-32 Architectures Optimization Reference Manual

INSTRUCTION LATENCY AND THROUGHPUTTable C-8. MMX Technology 64-bit Instructions (Contd.)Instruction Latency 1 ThroughputDisplayFamily_DisplayModel06_0FH06_0EH06_0DH06_09H06_0FH06_0EH06_0DHMOVQ mm, mm 1 1 1 1 0.5 0.5 0.5 0.5PACKSSWB/PACKSSDW/PA 1 1 1 1 1 1 1 1CKUSWB mm, mmPADDB/PADDW/PADDD 1 1 1 1 0.33 1 1 1mm, mmPADDSB/PADDSW/PADDUSB/PADDUSW mm,mm1 1 1 1 0.33 1 1 1PAND mm, mm 1 1 1 1 0.33 0.5 0.5 0.5PANDN mm, mm 1 1 1 1 0.33 0.5 0.5 0.5PCMPEQB/PCMPEQD 1 1 1 1 0.33 0.5 0.5 0.5PCMPEQW mm, mmPCMPGTB/PCMPGTD/ 1 1 1 1 0.33 0.5 0.5 0.5PCMPGTW mm, mmPMADDWD mm, mm 3 3 3 3 1 1 1 1PMULHW/PMULLW 3 3 3 3 3 1 1 1 1mm, mmPOR mm, mm 1 1 1 1 0.33 0.5 0.5 0.5PSLLQ/PSLLW/1 1 1 1 1 1 1 1PSLLD mm, mm/imm8PSRAW/PSRAD mm, 1 1 1 1 1 1 1 1mm/imm8PSRLQ/PSRLW/PSRLD 1 1 1 1 1 1 1 1mm, mm/imm8PSUBB/PSUBW/PSUBD 1 1 1 1 0.33 0.5 0.5 0.5mm, mmPSUBSB/PSUBSW/PSUBU 1 1 1 1 0.33 0.5 0.5 0.5SB/PSUBUSW mm, mmPUNPCKHBW/PUNPCKHW 1 1 1 1 1 1 1 1D/PUNPCKHDQ mm, mmPUNPCKLBW/PUNPCKLWD 1 1 1 1 1 1 1 1/PUNPCKLDQ mm, mmPXOR mm, mm 1 1 1 1 0.33 0.5 0.5 0.5EMMS 1 6 6 6 5 5 5See Appendix C.3.2, “Table Footnotes”06_09HC-20