Intel® 64 and IA-32 Architectures Optimization Reference Manual

INSTRUCTION LATENCY AND THROUGHPUT— The FP_EXECUTE unit is actually a cluster of execution units, roughlyconsisting of seven separate execution units.— The FP_ADD unit handles x87 and SIMD floating-point add and subtractoperation.— The FP_MUL unit handles x87 and SIMD floating-point multiply operation.— The FP_DIV unit handles x87 and SIMD floating-point divide square-rootoperations.— The MMX_SHFT unit handles shift and rotate operations.— The MMX_ALU unit handles SIMD integer ALU operations.— The MMX_MISC unit handles reciprocal MMX computations and some integeroperations.— The FP_MISC designates other execution units in port 1 that are separatedfrom the six units listed above.3. It may be possible to construct repetitive calls to some Intel 64 and IA-32instructions in code sequences to achieve latency that is one or two clock cyclesfaster than the more realistic number listed in this table.4. Latency and Throughput of transcendental instructions can vary substantially in adynamic execution environment. Only an approximate value or a range of valuesare given for these instructions.5. The FXCH instruction has 0 latency in code sequences. However, it is limited to anissue rate of one instruction per clock cycle.6. The load constant instructions, FINCSTP, and FDECSTP have 0 latency in codesequences.7. Selection of conditional jump instructions should be based on the recommendationof section Section 3.4.1, “Branch Prediction Optimization,” to improve thepredictability of branches. When branches are predicted successfully, the latencyof jcc is effectively zero.8. RCL/RCR with shift count of 1 are optimized. Using RCL/RCR with shift countother than 1 will be executed more slowly. This applies to the Pentium 4 and IntelXeon processors.C.3.3Latency and Throughput with Memory OperandsTypically, instructions with a memory address as the source operand, add one moreμop to the “reg, reg” instructions. However, the throughput in most cases remainsthe same because the load operation utilizes port 2 without affecting port 0 or port 1.Many instructions accept a memory address as either the source operand or as thedestination operand. The former is commonly referred to as a load operation, whilethe latter a store operation.C-26