IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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OPTIMIZING FOR SIMD INTEGER APPLICATIONS5.6.7 Packed Max/Min of Signed Word and Unsigned Byte5.6.7.1 Signed WordThe PMAXSW instruction returns the maximum between four signed words in eitherof two SIMD registers, or one SIMD register and a memory location.The PMINSW instruction returns the minimum between the four signed words ineither of two SIMD registers, or one SIMD register and a memory location.5.6.7.2 Unsigned ByteThe PMAXUB instruction returns the maximum between the eight unsigned bytes ineither of two SIMD registers, or one SIMD register and a memory location.The PMINUB instruction returns the minimum between the eight unsigned bytes ineither of two SIMD registers, or one SIMD register and a memory location.5.6.8 Packed Multiply High UnsignedThe PMULHUW/PMULHW instruction multiplies the unsigned/signed words in thedestination operand with the unsigned/signed words in the source operand. Thehigh-order 16 bits of the 32-bit intermediate results are written to the destinationoperand.5.6.9 Packed Sum of Absolute DifferencesThe PSADBW instruction computes the absolute value of the difference of unsignedbytes for either two SIMD registers, or one SIMD register and a memory location.The differences are then summed to produce a word result in the lower 16-bit field,and the upper three words are set to zero. See Figure 5-9.5-28
OPTIMIZING FOR SIMD INTEGER APPLICATIONS63MM/m640X8 X7 X6 X5 X4 X3 X2 X163- - - - - - - -MM063Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1= = = = = = = =TempT8 T7 T6 T5 T4 T3 T2 T1063MM00..0 0..0 0..0 T1+T2+T3+T4+T5+T6+T7+T8OM15167Figure 5-9. PSADBW Instruction ExampleThe subtraction operation presented above is an absolute difference. That is,T = ABS(X-Y). Byte values are stored in temporary space, all values are summedtogether, and the result is written to the lower word of the destination register.5.6.10 Packed Average (Byte/Word)The PAVGB and PAVGW instructions add the unsigned data elements of the sourceoperand to the unsigned data elements of the destination register, along with a carryin.The results of the addition are then independently shifted to the right by one bitposition. The high order bits of each element are filled with the carry bits of the correspondingsum.The destination operand is an SIMD register. The source operand can either be anSIMD register or a memory operand.The PAVGB instruction operates on packed unsigned bytes and the PAVGW instructionoperates on packed unsigned words.5-29
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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OPTIMIZING CACHE USAGE• If a proc
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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APPLICATION PERFORMANCE TOOLSThe /f
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APPLICATION PERFORMANCE TOOLSTable
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APPLICATION PERFORMANCE TOOLSA.1.6.
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSprogra
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APPLICATION PERFORMANCE TOOLSThe Li
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APPLICATION PERFORMANCE TOOLSA.5 IN
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USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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