IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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USING PERFORMANCE MONITORING EVENTSMetricNon-prefetch ReadsUnderway from theprocessor 2All UC Underwayfrom the processor 2Table B-5. Performance Metrics - Bus (Contd.)DescriptionAccrued sum of thedurations of read(includes RFOs butexcludes prefetches)transactions thatoriginate from thisprocessorDivide by “Reads Nonprefetchfrom theprocessor” to get Nonprefetchread requestlatency.Also beware ofdifferent recipes inmask bits for Pentium4 and Intel Xeonprocessors betweenCPUID model fieldvalue of 2 and modelvalue less than 2.Accrued sum of thedurations of all UCtransactions by thisprocessorDivide by “All UC fromthe processor” to getUC request latency.Also beware ofdifferent recipes inmask bits for Pentium4 and Intel Xeonprocessors betweenCPUID model fieldvalue of 2 and modelvalue less than 2.Event Name or MetricExpressionIOQ_active_entriesIOQ_active_entriesEvent Mask ValueRequired1a. ReqA0, ALL_READ,OWN (CPUID model = 2).1a. ReqA0, MEM_UC,OWN (CPUID model = 2)B-22
USING PERFORMANCE MONITORING EVENTSMetricAll WC Underwayfrom the processor 2Bus WritesUnderway from theprocessor 2Table B-5. Performance Metrics - Bus (Contd.)DescriptionAccrued sum of thedurations of all WCtransactions by thisprocessor.Divide by “All WC fromthe processor” to getWC request latency.Also beware ofdifferent recipes inmask bits for Pentium4 and Intel Xeonprocessors betweenCPUID model fieldvalue of 2 and modelvalue less than 2.Accrued sum of thedurations of all writetransactions by thisprocessorDivide by “Writes fromthe Processor” to getbus write requestlatency.Also beware ofdifferent recipes inmask bits for Pentium4 and Intel Xeonprocessors betweenCPUID model fieldvalue of 2 and modelvalue less than 2.Event Name or MetricExpressionIOQ_active_entriesIOQ_active_entriesEvent Mask ValueRequired1a. ReqA0, MEM_WC,OWN (CPUID model = 2)1a. 1a. ReqA0,ALL_WRITE, OWN(CPUID model < 2);1b. ReqA0, ALL_WRITE,MEM_WB, MEM_WT,MEM_WP, MEM_WC,MEM_UC, OWN(CPUID model >= 2).B-23
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESpred
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GENERAL OPTIMIZATION GUIDELINESIn t
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESmiss
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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OPTIMIZING CACHE USAGE• If a proc
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
Page 340 and 341: POWER OPTIMIZATION FOR MOBILE USAGE
Page 354 and 355: APPLICATION PERFORMANCE TOOLSThe /f
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Page 370 and 371: USING PERFORMANCE MONITORING EVENTS
Page 432 and 433: INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUTT
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSto
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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