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Intel® 64 and IA-32 Architectures Optimization Reference Manual

Intel® 64 and IA-32 Architectures Optimization Reference Manual

Intel® 64 and IA-32 Architectures Optimization Reference Manual

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POWER OPTIMIZATION FOR MOBILE USAGES10.3 ACPI C-STATESWhen computational dem<strong>and</strong>s are less than 100%, part of the time the processor isdoing useful work <strong>and</strong> the rest of the time it is idle. For example, the processor couldbe waiting on an application time-out set by a Sleep() function, waiting for a webserver response, or waiting for a user mouse click. Figure 10-2 illustrates the relationshipbetween active <strong>and</strong> idle time.When an application moves to a wait state, the OS issues a HLT instruction <strong>and</strong> theprocessor enters a halted state in which it waits for the next interrupt. The interruptmay be a periodic timer interrupt or an interrupt that signals an event.Figure 10-2. Active Time Versus Halted Time of a ProcessorAs shown in the illustration of Figure 10-2, the processor is in either active or idle(halted) state. ACPI defines four C-state types (C0, C1, C2 <strong>and</strong> C3). ProcessorspecificC states can be mapped to an ACPI C-state type via ACPI st<strong>and</strong>ard mechanisms.The C-state types are divided into two categories: active (C0), in which theprocessor consumes full power; <strong>and</strong> idle (C1-3), in which the processor is idle <strong>and</strong>may consume significantly less power.The index of a C-state type designates the depth of sleep. Higher numbers indicate adeeper sleep state <strong>and</strong> lower power consumption. They also require more time towake up (higher exit latency).C-state types are described below:• C0 — The processor is active <strong>and</strong> performing computations <strong>and</strong> executinginstructions.• C1 — This is the lowest-latency idle state, which has very low exit latency. In theC1 power state, the processor is able to maintain the context of the systemcaches.• C2 — This level has improved power savings over the C1 state. The mainimprovements are provided at the platform level.10-3

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