IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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GENERAL OPTIMIZATION GUIDELINES3.6.4 Store ForwardingThe processor’s memory system only sends stores to memory (including cache) afterstore retirement. However, store data can be forwarded from a store to a subsequentload from the same address to give a much shorter store-load latency.There are two kinds of requirements for store forwarding. If these requirements areviolated, store forwarding cannot occur and the load must get its data from the cache(so the store must write its data back to the cache first). This incurs a penalty that islargely related to pipeline depth of the underlying micro-architecture.The first requirement pertains to the size and alignment of the store-forwarding data.This restriction is likely to have high impact on overall application performance. Typically,a performance penalty due to violating this restriction can be prevented. Thestore-to-load forwarding restrictions vary from one microarchitecture to another.Several examples of coding pitfalls that cause store-forwarding stalls and solutions tothese pitfalls are discussed in detail in Section 3.6.4.1, “Store-to-Load-ForwardingRestriction on Size and Alignment.” The second requirement is the availability ofdata, discussed in Section 3.6.4.2, “Store-forwarding Restriction on Data Availability.”A good practice is to eliminate redundant load operations.It may be possible to keep a temporary scalar variable in a register and never write itto memory. Generally, such a variable must not be accessible using indirect pointers.Moving a variable to a register eliminates all loads and stores of that variable andeliminates potential problems associated with store forwarding. However, it alsoincreases register pressure.Load instructions tend to start chains of computation. Since the out-of-order engineis based on data dependence, load instructions play a significant role in the engine’sability to execute at a high rate. Eliminating loads should be given a high priority.If a variable does not change between the time when it is stored and the time whenit is used again, the register that was stored can be copied or used directly. If registerpressure is too high, or an unseen function is called before the store and the secondload, it may not be possible to eliminate the second load.Assembly/Compiler Coding Rule 46. (H impact, M generality) Passparameters in registers instead of on the stack where possible. Passing argumentson the stack requires a store followed by a reload. While this sequence is optimizedin hardware by providing the value to the load directly from the memory orderbuffer without the need to access the data cache if permitted by store-forwardingrestrictions, floating point values incur a significant latency in forwarding. Passingfloating point arguments in (preferably XMM) registers should save this long latencyoperation.Parameter passing conventions may limit the choice of which parameters are passedin registers which are passed on the stack. However, these limitations may be overcomeif the compiler has control of the compilation of the whole binary (using wholeprogramoptimization).3-50
GENERAL OPTIMIZATION GUIDELINES3.6.4.1 Store-to-Load-Forwarding Restriction on Size and AlignmentData size and alignment restrictions for store-forwarding apply to processors basedon Intel NetBurst microarchitecture, Intel Core microarchitecture, Intel Core 2 Duo,Intel Core Solo and Pentium M processors. The performance penalty for violatingstore-forwarding restrictions is less for shorter-pipelined machines than for IntelNetBurst microarchitecture.Store-forwarding restrictions vary with each microarchitecture. Intel NetBurstmicroarchitecture places more constraints than Intel Core microarchitecture on codegeneration to enable store-forwarding to make progress instead of experiencingstalls. Fixing store-forwarding problems for Intel NetBurst microarchitecture generallyalso avoids problems on Pentium M, Intel Core Duo and Intel Core 2 Duo processors.The size and alignment restrictions for store-forwarding in processors based onIntel NetBurst microarchitecture are illustrated in Figure 3-3.Load Aligned withStore Will ForwardNon-Forwarding(a) Small load afterLarge StoreStoreLoadPenalty(b) Size of Load >=StoreStoreLoadPenalty(c) Size of Load >=Store(s)StoreLoadPenalty(d) 128-bit ForwardMust Be 16-ByteAlignedStoreLoadPenalty16-ByteBoundaryOM15155Figure 3-3. Size and Alignment Restrictions in Store Forwarding3-51
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURES4.4.3
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEExample 9-11.
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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APPLICATION PERFORMANCE TOOLSThe /f
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APPLICATION PERFORMANCE TOOLSA.1.6.
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APPLICATION PERFORMANCE TOOLSExampl
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USING PERFORMANCE MONITORING EVENTS
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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