IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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OPTIMIZING CACHE USAGEExample 9-11. Memory Copy Using Hardware Prefetch and Bus Segmentation (Contd.)movntdq [edi+ecx+48],xmm3movntdq [edi+ecx+64],xmm4movntdq [edi+ecx+80],xmm5movntdq [edi+ecx+96],xmm6movntdq [edi+ecx+112],xmm7add ecx,128cmp ecx,BLOCK_SIZEjne cpy_loop}}add esi,ecxadd edi,ecxsub edx,ecxjnz main_loopsfence9.7.2.8 Performance Comparisons of Memory Copy RoutinesThe throughput of a large-region, memory copy routine depends on several factors:• Coding techniques that implements the memory copy task• Characteristics of the system bus (speed, peak bandwidth, overhead inread/write transaction protocols)• Microarchitecture of the processorA comparison of the two coding techniques discussed above and two un-optimizedtechniques is shown in Table 9-2.Processor, CPUIDSignature andFSB SpeedPentium Mprocessor,0x6Dn, 400Intel Core Soloand Intel CoreDuo processors,0x6En, 667Table 9-2. Relative Performance of Memory Copy RoutinesByte SequentialDWORDSequentialSW prefetch + 8byte streamingstore1.3X 1.2X 1.6X 2.5X3.3X 3.5X 2.1X 4.7X4KB-Block HWprefetch + 16byte streamingstores9-36
OPTIMIZING CACHE USAGEProcessor, CPUIDSignature andFSB SpeedPentium Dprocessor, 0xF4n,800Table 9-2. Relative Performance of Memory Copy Routines (Contd.)Byte SequentialDWORDSequentialSW prefetch + 8byte streamingstore3.4X 3.3X 4.9X 5.7X4KB-Block HWprefetch + 16byte streamingstoresThe baseline for performance comparison is the throughput (bytes/sec) of 8-MByteregion memory copy on a first-generation Pentium M processor (CPUID signature0x69n) with a 400-MHz system bus using byte-sequential technique similar to thatshown in Example 9-9. The degree of improvement relative to the performancebaseline for some recent processors and platforms with higher system bus speedusing different coding techniques are compared.The second coding technique moves data at 4-Byte granularity using REP stringinstruction. The third column compares the performance of the coding techniquelisted in Example 9-10. The fourth column of performance compares the throughputof fetching 4-KBytes of data at a time (using hardware prefetch to aggregate busread transactions) and writing to memory via 16-Byte streaming stores.Increases in bus speed is the primary contributor to throughput improvements. Thetechnique shown in Example 9-11 will likely take advantage of the faster bus speedin the platform more efficiently. Additionally, increasing the block size to multiples of4-KBytes while keeping the total working set within the second-level cache canimprove the throughput slightly.The relative performance figure shown in Table 9-2 is representative of cleanmicroarchitectural conditions within a processor (e.g. looping s simple sequence ofcode many times). The net benefit of integrating a specific memory copy routine intoan application (full-featured applications tend to create many complicated microarchitecturalconditions) will vary for each application.9.7.3 Deterministic Cache ParametersIf CPUID supports the deterministic parameter leaf, software can use the leaf toquery each level of the cache hierarchy. Enumeration of each cache level is by specifyingan index value (starting form 0) in the ECX register (see “CPUID-CPU Identification”in Chapter 3 of the Intel® 64 and IA-32 Architectures Software Developer’sManual, Volume 2A).The list of parameters is shown in Table 9-3.9-37
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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Page 278 and 279: MULTICORE AND HYPER-THREADING TECHN
Page 294 and 295: OPTIMIZING CACHE USAGE• Take adva
Page 296 and 297: OPTIMIZING CACHE USAGEHardware pref
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Page 304 and 305: OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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Page 308 and 309: OPTIMIZING CACHE USAGETimeExecution
Page 310 and 311: OPTIMIZING CACHE USAGEschedule pref
Page 312 and 313: OPTIMIZING CACHE USAGEtime is large
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Page 334 and 335: 64-BIT MODE CODING GUIDELINESAssemb
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Page 338 and 339: 64-BIT MODE CODING GUIDELINES9-6
Page 340 and 341: POWER OPTIMIZATION FOR MOBILE USAGE
Page 354 and 355: APPLICATION PERFORMANCE TOOLSThe /f
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUT
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSto
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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