Intel® 64 and IA-32 Architectures Optimization Reference Manual

INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURESSometimes a modified cache line has to be evicted to make space for a new cacheline. The modified cache line is evicted in parallel to bringing the new data and doesnot require additional latency. However, when data is written back to memory, theeviction uses cache bandwidth and possibly bus bandwidth as well. Therefore, whenmultiple cache misses require the eviction of modified lines within a short time, thereis an overall degradation in cache response time.2.1.5.2 StoresWhen an instruction writes data to a memory location that has WB memory type, theprocessor first ensures that the line is in Exclusive or Modified state in its own DCU.The processor looks for the cache line in the following locations, in the specifiedorder:1. DCU of initiating core2. DCU of the other core and L2 cache3. System memoryThe cache line is taken from the DCU of the other core only if it is modified, ignoringthe cache line availability or state in the L2 cache. After reading for ownership iscompleted, the data is written to the first-level data cache and the line is marked asmodified.Reading for ownership and storing the data happens after instruction retirement andfollows the order of retirement. Therefore, the store latency does not effect the storeinstruction itself. However, several sequential stores may have cumulative latencythat can affect performance. Table 2-4 presents store latencies depending on theinitial cache line location.2.2 INTEL NETBURST ® MICROARCHITECTUREThe Pentium 4 processor, Pentium 4 processor Extreme Edition supporting Hyper-Threading Technology, Pentium D processor, and Pentium processor Extreme Editionimplement the Intel NetBurst microarchitecture. Intel Xeon processors that implementIntel NetBurst microarchitecture can be identified using CPUID (familyencoding 0FH).This section describes the features of the Intel NetBurst microarchitecture and itsoperation common to the above processors. It provides the technical backgroundrequired to understand optimization recommendations and the coding rulesdiscussed in the rest of this manual. For implementation details, including instructionlatencies, see Appendix C, “Instruction Latency and Throughput.”Intel NetBurst microarchitecture is designed to achieve high performance for integerand floating-point computations at high clock rates. It supports the followingfeatures:• hyper-pipelined technology that enables high clock rates2-19