IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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INSTRUCTION LATENCY AND THROUGHPUTTable C-10. General Purpose Instructions (Contd.)Instruction Latency 1 Throughput Execution Unit 2DisplayFamily_DisplayModel 0F_03H 0F_02H 0F_03H 0F_02H 0F_02HRCL/RCR reg, 1 8 6 4 1 1ROL/ROR 1 4 0.5 1RET 8 1 MEM_LOAD,ALUSAHF 1 0.5 0.5 0.5 ALUSAL/SAR/SHL/SHR 1 4 0.5 1SCAS 4 1.5 ALU,MEM_LOADSETcc 5 1.5 ALUSTI 36STOSB 5 2 ALU,MEM_STOREXCHG 1.5 1.5 1 1 ALUCALL 5 1 ALU,MEM_STOREMUL 10 14-18 1 5DIV 66-80 56-70 30 23See Appendix C.3.2, “Table Footnotes”Table C-10a. General Purpose InstructionsInstruction Latency 1 ThroughputDisplayFamily_DisplayModel06_0FH06_0EH06_0DH06_09H06_0FH06_0EH06_0DHADC/SBB reg, reg 2 2 2 2 0.33 2 2 2ADC/SBB reg, imm 2 1 1 1 0.33 0.5 0.5 0.5ADD/SUB 1 1 1 1 0.33 0.5 0.5 0.5AND/OR/XOR 1 1 1 1 0.33 0.5 0.5 0.5BSF/BSR 2 2 2 2 1 1 1 1BSWAP 2 2 2 2 0.5 1 1 1BT 1 0.33BTC/BTR/BTS 1 1 1 1 0.33 0.5 0.5 0.5CBW 1 0.3306_09HC-24
INSTRUCTION LATENCY AND THROUGHPUTTable C-10a. General Purpose Instructions (Contd.)Instruction Latency 1 ThroughputDisplayFamily_DisplayModel06_0FH06_0EH06_0DH06_09H06_0FH06_0EH06_0DHCLC/CMC 1 0.33CLI 9 11 11 11 9 11 11 11CMOV 2 0.5CMP/TEST 1 1 1 1 0.5 0.5 0.5 0.5DEC/INC 1 1 1 1 0.33 0.5 0.5 0.5IMUL r32 3 4 4 4 0.5 1 1 1IMUL imm32 3 4 4 4 0.5 1 1 1IDIV 22 22 38 22 22 38MOVSB/MOVSW 1 1 1 1 0.33 0.5 0.5 0.5MOVZB/MOVZW 1 1 1 1 0.33 0.5 0.5 0.5NEG/NOT/NOP 1 1 1 1 0.33 0.5 0.5 0.5PUSH 3 3 3 3 1 1 1 1RCL/RCR 1 1 1 1 1 1ROL/ROR 1 1 1 1 0.33 1 1 1SAHF 1 1 1 1 0.33 0.5 0.5 0.5SAL/SAR/SHL/SHR 1 0.33SETcc 1 1 1 1 0.33 0.5 0.5 0.5XCHG 3 2 2 2 1 1 1 1See Appendix C.3.2, “Table Footnotes”06_09HC.3.2Table FootnotesThe following footnotes refer to all tables in this appendix.1. Latency information for many instructions that are complex (> 4 μops) areestimates based on conservative (worst-case) estimates. Actual performance ofthese instructions by the out-of-order core execution unit can range fromsomewhat faster to significantly faster than the latency data shown in thesetables.2. The names of execution units apply to processor implementations of the IntelNetBurst microarchitecture with a CPUID signature of family 15, model encoding= 0, 1, 2. They include: ALU, FP_EXECUTE, FPMOVE, MEM_LOAD, MEM_STORE.See Figure 2-5 for execution units and ports in the out-of-order core. Note thefollowing:C-25
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESpred
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GENERAL OPTIMIZATION GUIDELINESIn t
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESmiss
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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OPTIMIZING CACHE USAGE• If a proc
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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APPLICATION PERFORMANCE TOOLSThe /f
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APPLICATION PERFORMANCE TOOLSTable
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APPLICATION PERFORMANCE TOOLSA.1.6.
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSprogra
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APPLICATION PERFORMANCE TOOLSThe Li
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APPLICATION PERFORMANCE TOOLSA.5 IN
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USING PERFORMANCE MONITORING EVENTS
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Page 404 and 405: USING PERFORMANCE MONITORING EVENTS
Page 432 and 433: INSTRUCTION LATENCY AND THROUGHPUTW
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Page 458 and 459: INSTRUCTION LATENCY AND THROUGHPUTC
Page 460 and 461: STACK ALIGNMENTThe solution to this
Page 462 and 463: STACK ALIGNMENTExample D-1. Aligned
Page 464 and 465: STACK ALIGNMENTExample D-2. Aligned
Page 466 and 467: STACK ALIGNMENTD-8
Page 468 and 469: SUMMARY OF RULES AND SUGGESTIONSret
Page 470 and 471: SUMMARY OF RULES AND SUGGESTIONSfou
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Page 476 and 477: SUMMARY OF RULES AND SUGGESTIONSCor
Page 478 and 479: SUMMARY OF RULES AND SUGGESTIONSE-1
Page 480 and 481: INDEXsummary of rules, E-1tuning hi
Page 482 and 483: INDEXevent ratios, B-50execution co
Page 484 and 485: INDEXprefetching, 8-5SFENCE instruc
Page 486 and 487: INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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Page 490: Intel Corp.999 CANADA PLACE,Suite 4
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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