IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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64-BIT MODE CODING GUIDELINESinstruction is not the optimal implementation if a 64-bit result is desired. Use theextended registers.For example, the following code sequence loads the 32-bit values sign-extended intothe 64-bit registers and performs a multiply:movsx rax, DWORD PTR[x]movsx rcx, DWORD PTR[y]imul rax, rcxThe 64-bit version above is more efficient than using the following 32-bit version:mov eax, DWORD PTR[x]mov ecx, DWORD PTR[y]imul ecxIn the 32-bit case above, EAX is required to be a source. The result ends up in theEDX:EAX pair instead of in a single 64-bit register.Assembly/Compiler Coding Rule 69. (ML impact, M generality) Use the64-bit versions of multiply for 32-bit integer multiplies that require a 64 bit result.To add two 64-bit numbers in 32-bit legacy mode, the add instruction followed by theaddc instruction is used. For example, to add two 64-bit variables (X and Y), thefollowing four instructions could be used:mov eax, DWORD PTR[X]mov edx, DWORD PTR[X+4]add eax, DWORD PTR[Y]adc edx, DWORD PTR[Y+4]The result will end up in the two-register EDX:EAX.In 64-bit mode, the above sequence can be reduced to the following:mov rax, QWORD PTR[X]add rax, QWORD PTR[Y]The result is stored in rax. One register is required instead of two.Assembly/Compiler Coding Rule 70. (ML impact, M generality) Use the64-bit versions of add for 64-bit adds.9.3.2 CVTSI2SS and CVTSI2SDThe CVTSI2SS and CVTSI2SD instructions convert a signed integer in a generalpurposeregister or memory location to a single-precision or double-precisionfloating-point value. The signed integer can be either 32-bits or 64-bits.In processors based on Intel NetBurst microarchitecture, the 32-bit version willexecute from the trace cache; the 64-bit version will result in a microcode flow fromthe microcode ROM and takes longer to execute. In most cases, the 32-bit versionsof CVTSI2SS and CVTSI2SD is sufficient.9-4
64-BIT MODE CODING GUIDELINESIn processors based on Intel Core microarchitecture, CVTSI2SS and CVTSI2SD areimproved significantly over those in Intel NetBurst microarchitecture, in terms oflatency and throughput. The improvements applies equally to 64-bit and 32-bitversions.9.3.3 Using Software PrefetchIntel recommends that software developers follow the recommendations inChapter 3 and Chapter 7 when considering the choice of organizing data accesspatterns to take advantage of the hardware prefetcher (versus using softwareprefetch).Assembly/Compiler Coding Rule 71. (L impact, L generality) If softwareprefetch instructions are necessary, use the prefetch instructions provided by SSE.9-5
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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Page 286 and 287: MULTICORE AND HYPER-THREADING TECHN
Page 294 and 295: OPTIMIZING CACHE USAGE• Take adva
Page 296 and 297: OPTIMIZING CACHE USAGEHardware pref
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Page 304 and 305: OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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Page 308 and 309: OPTIMIZING CACHE USAGETimeExecution
Page 310 and 311: OPTIMIZING CACHE USAGEschedule pref
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Page 324 and 325: OPTIMIZING CACHE USAGE9.7.2.3 Concl
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Page 328 and 329: OPTIMIZING CACHE USAGEExample 9-11.
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Page 332 and 333: OPTIMIZING CACHE USAGE• If a proc
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Page 338 and 339: 64-BIT MODE CODING GUIDELINES9-6
Page 340 and 341: POWER OPTIMIZATION FOR MOBILE USAGE
Page 354 and 355: APPLICATION PERFORMANCE TOOLSThe /f
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Page 366 and 367: APPLICATION PERFORMANCE TOOLSThe Li
Page 368 and 369: APPLICATION PERFORMANCE TOOLSA.5 IN
Page 370 and 371: USING PERFORMANCE MONITORING EVENTS
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USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSto
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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