Intel® 64 and IA-32 Architectures Optimization Reference Manual

OPTIMIZING CACHE USAGEapproach to separate bus read and write transactions. See Section 3.6.11, “MinimizingBus Latency.”The technique employs two stages. In the first stage, a block of data is read frommemory to the cache sub-system. In the second stage, cached data are written totheir destination using streaming stores.Example 9-11. Memory Copy Using Hardware Prefetch and Bus Segmentationvoid block_prefetch(void *dst,void *src){ _asm {mov edi,dstmov esi,srcmov edx,SIZEalign 16main_loop:xor ecx,ecxalign 16}prefetch_loop:movaps xmm0, [esi+ecx]movaps xmm0, [esi+ecx+64]add ecx,128cmp ecx,BLOCK_SIZEjne prefetch_loopxor ecx,ecxalign 16cpy_loop:movdqa xmm0,[esi+ecx]movdqa xmm1,[esi+ecx+16]movdqa xmm2,[esi+ecx+32]movdqa xmm3,[esi+ecx+48]movdqa xmm4,[esi+ecx+64]movdqa xmm5,[esi+ecx+16+64]movdqa xmm6,[esi+ecx+32+64]movdqa xmm7,[esi+ecx+48+64]movntdq [edi+ecx],xmm0movntdq [edi+ecx+16],xmm1movntdq [edi+ecx+32],xmm29-35