IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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APPLICATION PERFORMANCE TOOLSA.5 INTEL ® SOFTWARE COLLEGEYou can find information on classroom training offered by the Intel Software Collegeat http://developer.intel.com/software/college. Find general information for developersat http://softwarecommunity.intel.com/isn/home/.A-16
APPENDIX BUSING PERFORMANCE MONITORING EVENTSPerformance monitoring events provide facilities to characterize the interactionbetween programmed sequences of instructions and microarchitectural subsystems.Performance monitoring events are described in Chapter 18 and AppendixA of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.The first part of this chapter provides information on how to use performance eventsspecific to processors based on the Intel NetBurst microarchitecture. Section B.5discusses similar topics for performance events available on Intel Core Solo and IntelCore Duo processors.B.1 PENTIUM ® 4 PROCESSOR PERFORMANCE METRICSThe descriptions of Intel Pentium 4 processor performance metrics use terminologythat is specific to the Intel NetBurst microarchitecture and to implementations in thePentium 4 and Intel Xeon processors. The performance metrics in Table B-1 throughTable B-13 apply to processors with a CPUID signature that matches family encoding15, mode encoding 0, 1, 2, 3, 4, or 6. Several new performance metrics are availableto IA-32 processors with a CPUID signature that matches family encoding 15, modeencoding 3; the new metrics are listed in Table B-11.The performance metrics listed in Tables B-1 through B-7 may be applicable toprocessors that support HT Technology. See Appendix B.4, “Using PerformanceMetrics with Hyper-Threading Technology.”B.1.1Pentium ® 4 Processor-Specific TerminologyB.1.1.1Bogus, Non-bogus, RetireBranch mispredictions incur a large penalty on microprocessors with deep pipelines.In general, the direction of branches can be predicted with a high degree of accuracyby the front end of the Intel Pentium 4 processor, such that most computations canbe performed along the predicted path while waiting for the resolution of the branch.In the event of a misprediction, instructions and μops that were scheduled to executealong the mispredicted path must be cancelled. These instructions and μops arereferred to as bogus instructions and bogus μops. A number of Pentium 4 processorperformance monitoring events, for example, instruction_ retired and μops_retired,can count instructions or mops that are retired based on the characterization ofbogus versus non-bogus.Vol. 1 B-1
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESmiss
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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Page 370 and 371: USING PERFORMANCE MONITORING EVENTS
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USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUTo
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INSTRUCTION LATENCY AND THROUGHPUTT
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSto
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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