Intel® 64 and IA-32 Architectures Optimization Reference Manual

USING PERFORMANCE MONITORING EVENTSB.7.7.3Software PrefetchingThe events for software prefetching cover each level of prefetching separately.40. Useful PrefetchNTA Ratio: SSE_PRE_MISS.NTA / SSE_PRE_EXEC.NTA * 10041. Useful PrefetchT0 Ratio: SSE_PRE_MISS.L1 / SSE_PRE_EXEC.L1 * 10042. Useful PrefetchT1 and PrefetchT2 Ratio: SSE_PRE_MISS.L2 / SSE_PRE_EXEC.L2* 100A low value for any of the prefetch usefulness ratios indicates that some of the SSEprefetch instructions prefetch data that is already in the caches.43. Late PrefetchNTA Ratio: LOAD_HIT_PRE / SSE_PRE_EXEC.NTA44. Late PrefetchT0 Ratio: LOAD_HIT_PRE / SSE_PRE_EXEC.L145. Late PrefetchT1 and PrefetchT2 Ratio: LOAD_HIT_PRE / SSE_PRE_EXEC.L2A high value for any of the late prefetch ratios indicates that software prefetchinstructions are issued too late and the load operations that use the prefetched dataare waiting for the cache line to arrive.B.7.8Memory Sub-system - TLB Miss Ratios46. TLB miss penalty: PAGE_WALKS.CYCLES / CPU_CLK_UNHALTED.CORE * 100A high value for the TLB miss penalty ratio indicates that many cycles are spent onTLB misses. Reducing the number of TLB misses may improve performance. Thisratio does not include DTLB0 miss penalties (see Ratio 37).The following ratios help to focus on the kind of memory accesses that cause TLBmisses most frequently See “ITLB Miss Rate” (Ratio 6) for TLB misses due to instructionfetch.47. DTLB Miss Rate: DTLB_MISSES.ANY / INST_RETIRED.ANYA high value for DTLB Miss Rate indicates that the code accesses too many datapages within a short time, and causes many Data TLB misses.48. DTLB Miss Rate due to Loads: DTLB_MISSES.MISS_LD / INST_RETIRED.ANYA high value for DTLB Miss Rate due to Loads indicates that the code accesses loadsdata from too many pages within a short time, and causes many Data TLB misses.DTLB misses due to load operations may have a significant impact, since the DTLBmiss increases the load operation latency. This ratio does not include DTLB0 misspenalties (see Ratio 37).To precisely locate load instructions that caused DTLB misses you can use the preciseevent MEM_LOAD_RETIRE.DTLB_MISS.49. DTLB Miss Rate due to Stores: DTLB_MISSES.MISS_ST / INST_RETIRED.ANYA high value for DTLB Miss Rate due to Stores indicates that the code accesses toomany data pages within a short time, and causes many Data TLB misses due to storeB-59