IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW, 5-28PMINUB, 5-28PMOVMSKB, 5-14PMULHUW, 5-28PMULHW, 5-28PMULUDQ, 5-30PSADBW, 5-28PSHUF, 5-15PSHUFB, 5-21, 5-23PSHUFLW, 5-17PSLLDQ, 5-31PSRLDQ, 5-31PSUBQ, 5-30PUNPCHQDQ, 5-18PUNPCKLQDQ, 5-18simplified 3D geometry pipeline, 8-15simplified clipping to an arbitrary signed range, 5-27single vs multi-pass execution, 8-27sleep transitions, 10-7smart cache, 2-36SoA format, 4-20software write-combining, 8-30spin-loops, 10-6optimization, 3-9PAUSE instruction, 3-9related information, 1-3SSE, 2-48SSE2, 2-48SSE3, 2-49SSSE3, 2-49stackaligned EDP-based frames, D-4aligned ESP-based frames, D-3alignment 128-bit SIMD, 4-15alignment stack, 3-59dynamic alignment, 3-59frame optimizations, D-6inlined assembly & EBX, D-7Intel C++ Compiler support for, D-1overview, D-1state transitions, 10-2static branch prediction algorithm, 3-10static power, 10-1static prediction, 3-9streaming stores, 8-7coherent requests, 8-9improving performance, 8-7non-coherent requests, 8-9strip-mining, 4-22, 4-23, 8-24, 8-25prefetch considerations, 8-26structuresaligning, 3-56suggestions, E-1summary of coding rules, E-1swizzling dataSee data swizzling.system bus optimization, 7-23Ttagging, B-2tagging mechanismsexecution_event, B-37front_end_event, B-37replay_event, B-35time-based sampling, A-11time-consuming innermost loops, 8-5time-stamp counter, B-5non-sleep clock ticks, B-5RDTSC instruction, B-5sleep pin, B-5TLB. See transaction lookaside buffertrace cacheevents, B-30transaction lookaside buffer, 8-<strong>32</strong>transcendental functions, 3-86Uunpack instructions, 5-10UNPACKHPS instruction, 6-7UNPACKLPS instruction, 6-7UNPCKHPS instruction, 6-10UNPCKLPS instruction, 6-10unrolling loopsbenefits of, 3-15code examples, 3-16limitation of, 3-15unsigned unpack, 5-6using MMX code for copy, shuffling, 6-12Vvector class library, 4-12vectorized codeauto generation, A-6automatic vectorization, 4-12high-level examples, A-6parallelism, 4-7SIMD architecture, 4-7switch options, A-4vertical vs horizontal computation, 6-3WWaitForSingleObject(), 10-6WaitMessage(), 10-6weakly ordered stores, 8-7WiFi, 10-7WLAN, 10-7workload characterizationretirement throughput, A-11Index-8
INDEXwrite-combiningbuffer, 8-30memory, 8-30semantics, 8-8XXCHG EAX,EAX, support for, 3-31Index-9
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESpred
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GENERAL OPTIMIZATION GUIDELINESIn t
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESvalu
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESmiss
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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OPTIMIZING CACHE USAGE• If a proc
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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APPLICATION PERFORMANCE TOOLSThe /f
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APPLICATION PERFORMANCE TOOLSTable
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APPLICATION PERFORMANCE TOOLSA.1.6.
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSprogra
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APPLICATION PERFORMANCE TOOLSThe Li
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APPLICATION PERFORMANCE TOOLSA.5 IN
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USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUTo
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Page 460 and 461: STACK ALIGNMENTThe solution to this
Page 462 and 463: STACK ALIGNMENTExample D-1. Aligned
Page 464 and 465: STACK ALIGNMENTExample D-2. Aligned
Page 466 and 467: STACK ALIGNMENTD-8
Page 468 and 469: SUMMARY OF RULES AND SUGGESTIONSret
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Page 478 and 479: SUMMARY OF RULES AND SUGGESTIONSE-1
Page 480 and 481: INDEXsummary of rules, E-1tuning hi
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Page 490: Intel Corp.999 CANADA PLACE,Suite 4
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