Intel® 64 and IA-32 Architectures Optimization Reference Manual

GENERAL OPTIMIZATION GUIDELINESFor example, using a simple function that returns an input parameter (representativeof tight, short loops), the per-iteration cost of packing/unpacking may range fromslightly more than 7 cycles (the shuffle with store forwarding case, Example 3-22) to~0.9 cycles (accomplished by several test cases). Across 27 test cases (consisting ofone of the alternate packing methods, no result-simplification/simplification of either1 or 4 results, no stack optimization or with stack optimization), the average per-iterationcost of packing/unpacking is about 1.7 cycles.Generally speaking, packing method 2 and 3 (see Example 3-23) tend to be morerobust than packing method 1; the optimal choice of simplifying 1 or 4 results will beaffected by register pressure of the runtime and other relevant microarchitecturalconditions.Note that the numeric discussion of per-iteration cost of packing/packing is illustrativeonly. It will vary with test cases using a different base line code sequence and willgenerally increase if the non-vectorizable routine requires longer time to executebecause the number of loop iterations that can reside in flight in the execution coredecreases.3.6 OPTIMIZING MEMORY ACCESSESThis section discusses guidelines for optimizing code and data memory accesses. Themost important recommendations are:• Execute load and store operations within available execution bandwidth.• Enable forward progress of speculative execution.• Enable store forwarding to proceed.• Align data, paying attention to data layout and stack alignment.• Place code and data on separate pages.• Enhance data locality.• Use prefetching and cacheability control instructions.• Enhance code locality and align branch targets.• Take advantage of write combining.Alignment and forwarding problems are among the most common sources of largedelays on processors based on Intel NetBurst microarchitecture.3.6.1 Load and Store Execution BandwidthTypically, loads and stores are the most frequent operations in a workload, up to 40%of the instructions in a workload carrying load or store intent are not uncommon.Each generation of microarchitecture provides multiple buffers to support executingload and store operations while there are instructions in flight.3-46