IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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GENERAL OPTIMIZATION GUIDELINESPacked SIMD InstructionUnpackingUnvectorizable CodeSerial RoutinePackingPacked SIMD InstructionFigure 3-1. Generic Program Flow of Partially Vectorized CodeIt generally consists of five stages within the loop:• Prolog• Unpacking vectorized data structure into individual elements• Calling a non-vectorizable routine to process each element serially• Packing individual result into vectorized data structure• EpilogThis section discusses techniques that can reduce the cost and bottleneck associatedwith the packing/unpacking stages in these partially vectorize code.Example 3-22 shows a reference code template that is representative of partiallyvectorizable coding situations that also experience performance issues. The unvectorizableportion of code is represented generically by a sequence of calling a serialfunction named “foo” multiple times. This generic example is referred to as “shufflewith store forwarding”, because the problem generally involves an unpacking stagethat shuffles data elements between register and memory, followed by a packingstage that can experience store forwarding issue.There are more than one useful techniques that can reduce the store-forwardingbottleneck between the serialized portion and the packing stage. The following subsectionspresents alternate techniques to deal with the packing, unpacking, andparameter passing to serialized function calls.3-40
GENERAL OPTIMIZATION GUIDELINESExample 3-22. Reference Code Template for Partially Vectorizable Program// Prolog ///////////////////////////////push ebpmov ebp, esp// Unpacking ////////////////////////////sub ebp, 32and ebp, 0xfffffff0movaps [ebp], xmm0// Serial operations on components ///////sub ebp, 4mov eax, [ebp+4]mov [ebp], eaxcall foomov [ebp+16+4], eaxmov eax, [ebp+8]mov [ebp], eaxcall foomov [ebp+16+4+4], eaxmov eax, [ebp+12]mov [ebp], eaxcall foomov [ebp+16+8+4], eaxmov eax, [ebp+12+4]mov [ebp], eaxcall foomov [ebp+16+12+4], eax// Packing ///////////////////////////////movaps xmm0, [ebp+16+4]// Epilog ////////////////////////////////pop ebpret3-41
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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Page 63 and 64: INTEL® 64 AND IA-32 PROCESSOR ARCH
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURES4.3.1
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURES4.4.3
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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OPTIMIZING CACHE USAGE• If a proc
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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APPLICATION PERFORMANCE TOOLSThe /f
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APPLICATION PERFORMANCE TOOLSTable
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APPLICATION PERFORMANCE TOOLSA.1.6.
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSprogra
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APPLICATION PERFORMANCE TOOLSThe Li
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APPLICATION PERFORMANCE TOOLSA.5 IN
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USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUTo
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INSTRUCTION LATENCY AND THROUGHPUTT
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSto
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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