IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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APPLICATION PERFORMANCE TOOLSExample 10-4. Auto-Generated Code of Sign ConversionCompiler Switch QxWCompiler Switch QxT$B1$3:mov edx, _src[eax*4]add eax, 1test edx, edxjne $B1$5$B1$4:mov _dst[eax*4], 0jmp $B1$7ALIGN 4$B1$5:jge $B1$7$B1$6:mov edx, _dst[eax*4]neg edxmov _dst[eax*4], edx$B1$7:cmp eax, 1024jl $B1$3$B1$3:movdqa xmm0, _dst[eax*4]psignd xmm0, _src[eax*4]movdqa _dst[eax*4], xmm0add eax, 4cmp eax, 1024jb $B1$3Example 10-5. Data Conversionint dst[1024];unsigned char src[1024];for (i = 0; i < 1024; i++) {dst[i] = src[i]}A-8
APPLICATION PERFORMANCE TOOLSExample 10-6. Auto-Generated Code of Data ConversionCompiler Switch QxWCompiler Switch QxT$B1$2:xor eax, eaxpxor xmm0, xmm0$B1$3:movd xmm1, _src[eax]punpcklbw xmm1, xmm0punpcklwd xmm1, xmm0movdqa _dst[eax*4], xmm1add eax, 4cmp eax, 1024jb $B1$3$B1$2:movdqa xmm0, _2il0fl2t$1DDxor eax, eax$B1$3:movd xmm1, _src[eax]pshufb xmm1, xmm0movdqa _dst[eax*4], xmm1add eax, 4cmp eax, 1024jb $B1$3…_2il0fl2t$1DD0ffffff00H,0ffffff01H,0ffffff02H,0ffffff03HExample 10-7. Un-aligned Data Operation__declspec(align(16)) float src[1024], dst[1024];for(i = 2; i < 1024-2; i++)dst[i] = src[i-2] - src[i-1] - src[i+2 ];Intel Compiler can use PALIGNR to generate code to avoid penalties associated withunaligned loads.A-9
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESpred
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GENERAL OPTIMIZATION GUIDELINESIn t
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESvalu
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESmiss
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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Page 334 and 335: 64-BIT MODE CODING GUIDELINESAssemb
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Page 338 and 339: 64-BIT MODE CODING GUIDELINES9-6
Page 340 and 341: POWER OPTIMIZATION FOR MOBILE USAGE
Page 354 and 355: APPLICATION PERFORMANCE TOOLSThe /f
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Page 366 and 367: APPLICATION PERFORMANCE TOOLSThe Li
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Page 370 and 371: USING PERFORMANCE MONITORING EVENTS
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USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUTo
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INSTRUCTION LATENCY AND THROUGHPUTT
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSto
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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