IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONSExample 6-10. Horizontal Add Using Intrinsics with MOVHLPS/MOVLHPS (Contd.)tmm2 = _mm_movelh_ps(tmm2, tmm3); // tmm2 = C1 C2 D1 D2tmm3 = _mm_movehl_ps(tmm3, tmm4); // tmm3 = C3 C4 D3 D4tmm3 = _mm_add_ps(tmm3, tmm2); // tmm3 = C1+C3 C2+C4 D1+D3 D2+D4tmm6 = tmm3; // tmm6 = C1+C3 C2+C4 D1+D3 D2+D4tmm6 = _mm_shuffle_ps(tmm3, tmm5, 0xDD);// tmm6 = A1+A3 B1+B3 C1+C3 D1+D3tmm5 = _mm_shuffle_ps(tmm5, tmm6, 0x88);// tmm5 = A2+A4 B2+B4 C2+C4 D2+D4tmm6 = _mm_add_ps(tmm6, tmm5);// tmm6 = A1+A2+A3+A4 B1+B2+B3+B4// C1+C2+C3+C4 D1+D2+D3+D4_mm_store_ps(out, tmm6);}6.5.2 Use of CVTTPS2PI/CVTTSS2SI InstructionsThe CVTTPS2PI and CVTTSS2SI instructions encode the truncate/chop roundingmode implicitly in the instruction. They take precedence over the rounding modespecified in the MXCSR register. This behavior can eliminate the need to change therounding mode from round-nearest, to truncate/chop, and then back to roundnearestto resume computation.Avoid frequent changes to the MXCSR register since there is a penalty associatedwith writing this register. Typically, when using CVTTPS2P/CVTTSS2SI, roundingcontrol in MXCSR can always be set to round-nearest.6.5.3 Flush-to-Zero and Denormals-are-Zero ModesThe flush-to-zero (FTZ) and denormals-are-zero (DAZ) modes are not compatiblewith the IEEE Standard 754. They are provided to improve performance for applicationswhere underflow is common and where the generation of a denormalized resultis not necessary.See also: Section 3.8.2, “Floating-point Modes and Exceptions.”6.6 SIMD OPTIMIZATIONS AND MICROARCHITECTURESPentium M, Intel Core Solo and Intel Core Duo processors have a different microarchitecturethan Intel NetBurst microarchitecture. Intel Core microarchitecture offerssignificantly more efficient SIMD floating-point capability than previous microarchitectures.In addition, instruction latency and throughput of SSE3 instructions are significantlyimproved in Intel Core microarchitecture over previous microarchitectures.6-16
OPTIMIZING FOR SIMD FLOATING-POINT APPLICATIONS6.6.1 SIMD Floating-point Programming Using SSE3SSE3 enhances SSE and SSE2 with nine instructions targeted for SIMD floating-pointprogramming. In contrast to many SSE/SSE2 instructions offering homogeneousarithmetic operations on parallel data elements and favoring the vertical computationmodel, SSE3 offers instructions that performs asymmetric arithmetic operation andarithmetic operation on horizontal data elements.ADDSUBPS and ADDSUBPD are two instructions with asymmetric arithmeticprocessing capability (see Figure 6-5). HADDPS, HADDPD, HSUBPS and HSUBPDoffers horizontal arithmetic processing capability (see Figure 6-6). In addition:MOVSLDUP, MOVSHDUP and MOVDDUP load data from memory (or XMM register)and replicate data elements at once.X1X0Y1Y0ADDSUBX1 + Y1 X0 -Y0Figure 6-5. Asymmetric Arithmetic Operation of the SSE3 Instruction6-17
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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OPTIMIZING CACHE USAGE• If a proc
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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APPLICATION PERFORMANCE TOOLSThe /f
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APPLICATION PERFORMANCE TOOLSTable
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APPLICATION PERFORMANCE TOOLSA.1.6.
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSprogra
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APPLICATION PERFORMANCE TOOLSThe Li
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APPLICATION PERFORMANCE TOOLSA.5 IN
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USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUTo
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSto
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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Intel Corp.999 CANADA PLACE,Suite 4
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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