IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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INSTRUCTION LATENCY AND THROUGHPUTTable C-9. x87 Floating-point Instructions (Contd.)Instruction Latency 1 Throughput Execution Unit 2DisplayFamily_DisplayModel0F_03H 0F_02H 0F_03H 0F_02H 0F_02HFINCSTP/FDECSTP 6 0See Appendix C.3.2, “Table Footnotes”Table C-9a. x87 Floating-point InstructionsInstruction Latency 1 ThroughputDisplayFamily_DisplayModel06_0FH06_0EH06_0DH06_09H06_0FH06_0EH06_0DH06_09HFABS 1 1 1 1 1 1 1 1FADD 3 3 3 3 1 1 1FSUB 3 3 3 3 1 1 1 1FMUL 5 5 5 5 2 2 2 2FCOM 1 1 1 1 1 1 1 1FCHSFDIV Single Precision 18 17FDIV Double Precision 32 31FDIV Extended Precision 38 37FSQRT Single Precision 29 28FSQRT Double Precision 58 58 58 58 58 58 58 58F2XM1 4 69 69 69 67 67 67FCOS 4 119 119 119 117 117 117FPATAN 4 147 147 147 147 147 147FPTAN 4 123 123 123 83 83 83FSIN 4 119 119 119 116 116 116FSINCOS 4 119 119 119 85 85 85FYL2X 4 96 96 96 92 92 92FYL2XP1 4 98 98 98 93 93 93FSCALE 4 17 17 17 15 15 15FRNDINT 4 21 21 21 20 20 20FXCH 5FLDZ 6 1 1 1 1 1 1 1 1FINCSTP/FDECSTP 6 1 1 1 1 1 1C-22
INSTRUCTION LATENCY AND THROUGHPUTTable C-9a. x87 Floating-point Instructions (Contd.)Instruction Latency 1 ThroughputDisplayFamily_DisplayModel06_0FHSee Appendix C.3.2, “Table Footnotes”06_0EH06_0DH06_09H06_0FH06_0EH06_0DH06_09HTable C-10. General Purpose InstructionsInstruction Latency 1 Throughput Execution Unit 2DisplayFamily_DisplayModel 0F_03H 0F_02H 0F_03H 0F_02H 0F_02HADC/SBB reg, reg 8 8 3 3ADC/SBB reg, imm 8 6 2 2 ALUADD/SUB 1 0.5 0.5 0.5 ALUAND/OR/XOR 1 0.5 0.5 0.5 ALUBSF/BSR 16 8 2 4BSWAP 1 7 0.5 1 ALUBTC/BTR/BTS 8-9 1CLI 26CMP/TEST 1 0.5 0.5 0.5 ALUDEC/INC 1 1 0.5 0.5 ALUIMUL r32 10 14 1 3 FP_MULIMUL imm32 14 1 3 FP_MULIMUL 15-18 5IDIV 66-80 56-70 30 23IN/OUT 1
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESpred
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GENERAL OPTIMIZATION GUIDELINESIn t
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESmiss
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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OPTIMIZING CACHE USAGE• If a proc
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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APPLICATION PERFORMANCE TOOLSThe /f
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APPLICATION PERFORMANCE TOOLSTable
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APPLICATION PERFORMANCE TOOLSA.1.6.
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSprogra
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APPLICATION PERFORMANCE TOOLSThe Li
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APPLICATION PERFORMANCE TOOLSA.5 IN
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USING PERFORMANCE MONITORING EVENTS
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Page 402 and 403: USING PERFORMANCE MONITORING EVENTS
Page 432 and 433: INSTRUCTION LATENCY AND THROUGHPUTW
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Page 460 and 461: STACK ALIGNMENTThe solution to this
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Page 468 and 469: SUMMARY OF RULES AND SUGGESTIONSret
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Page 476 and 477: SUMMARY OF RULES AND SUGGESTIONSCor
Page 478 and 479: SUMMARY OF RULES AND SUGGESTIONSE-1
Page 480 and 481: INDEXsummary of rules, E-1tuning hi
Page 482 and 483: INDEXevent ratios, B-50execution co
Page 484 and 485: INDEXprefetching, 8-5SFENCE instruc
Page 486 and 487: INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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Page 490: Intel Corp.999 CANADA PLACE,Suite 4
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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