Intel® 64 and IA-32 Architectures Optimization Reference Manual

USING PERFORMANCE MONITORING EVENTSMetricTable B-3. Performance Metrics - Trace Cache and Front End (Contd.)Logical Processor 1Build ModeTrace Cache MissesTC to ROM TransfersSpeculative TC-BuiltμopsDescriptionIf a physical processorsupports only onelogical processor, alltraces are associatedwith logical processor0.Number of cycles thatthe trace and deliveryengine (TDE) isbuilding tracesassociated with logicalprocessor 1,regardless of operatingmodes of TDE fortraces associated withlogical processor 0This metric isapplicable only if aphysical processorsupports HTTechnology and hastwo logical processorsper package.Number of times thatsignificant delaysoccurred in order todecode instructionsand build a tracebecause of a TC missTwice the number oftimes that ROMmicrocode is accessedto decode complexinstructions instead ofbuilding|deliveringtracesDivide the count by 2to get the number ofoccurrence.Number of speculativeμops originating whenthe TC is in build modeEvent Name or MetricExpressionTC_deliver_modeBPU_fetch_requesttc_ms_xferμop_queue_writesEvent Mask ValueRequiredBB | SB | IBTCMISSCISCFROM_TC_BUILDB-11