Intel® 64 and IA-32 Architectures Optimization Reference Manual

INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES2.2.4.3 CachesThe Intel NetBurst microarchitecture supports up to three levels of on-chip cache. Atleast two levels of on-chip cache are implemented in processors based on the IntelNetBurst microarchitecture. The Intel Xeon processor MP and selected Pentium andIntel Xeon processors may also contain a third-level cache.The first level cache (nearest to the execution core) contains separate caches forinstructions and data. These include the first-level data cache and the trace cache(an advanced first-level instruction cache). All other caches are shared betweeninstructions and data.Levels in the cache hierarchy are not inclusive. The fact that a line is in level i doesnot imply that it is also in level i+1. All caches use a pseudo-LRU (least recently used)replacement algorithm.Table 2-5 provides parameters for all cache levels for Pentium and Intel Xeon Processorswith CPUID model encoding equals 0, 1, 2 or 3.Table 2-5. Pentium 4 and Intel Xeon Processor Cache ParametersLevel (Model)CapacityAssociativity(ways)Line Size(bytes)AccessLatency,Integer/floating-point(clocks)Write UpdatePolicyFirst (Model 0,1, 2)8 KB 4 64 2/9 write throughFirst (Model 3) 16 KB 8 64 4/12 write throughTC (All models) 12K µops 8 N/A N/A N/ASecond (Model0, 1, 2)256 KB or512 KB 18 64 27/7 write backSecond (Model3, 4)Second (Model3, 4, 6)1 MB 8 64 2 18/18 write back2 MB 8 64 2 20/20 write backThird (Model0, 1, 2)0, 512 KB,1MB or 2MB8 64 2 14/14 write backNOTES:1. Pentium 4 and Intel Xeon processors with CPUID model encoding value of 2 have a second levelcache of 512 KB.2. Each read due to a cache miss fetches a sector, consisting of two adjacent cache lines; a writeoperation is 64 bytes.2-28