IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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OPTIMIZING CACHE USAGEA characteristic feature of both single-pass and multi-pass execution is that a specifictrade-off exists depending on an algorithm’s implementation and use of a single-passor multiple-pass execution. See Figure 9-9.Multi-pass execution is often easier to use when implementing a general purposeAPI, where the choice of code paths that can be taken depends on the specific combinationof features selected by the application (for example, for 3D graphics, thismight include the type of vertex primitives used and the number and type of lightsources).With such a broad range of permutations possible, a single-pass approach would becomplicated, in terms of code size and validation. In such cases, each possiblepermutation would require a separate code sequence. For example, an object withfeatures A, B, C, D can have a subset of features enabled, say, A, B, D. This stagewould use one code path; another combination of enabled features would have adifferent code path. It makes more sense to perform each pipeline stage as a separatepass, with conditional clauses to select different features that are implementedwithin each stage. By using strip-mining, the number of vertices processed by eachstage (for example, the batch size) can be selected to ensure that the batch stayswithin the processor caches through all passes. An intermediate cached buffer isused to pass the batch of vertices from one stage or pass to the next one.Single-pass execution can be better suited to applications which limit the number offeatures that may be used at a given time. A single-pass approach can reduce theamount of data copying that can occur with a multi-pass engine. See Figure 9-9.9-28
OPTIMIZING CACHE USAGEstrip list80 vis60 invis40 vis80 vis40 visCullingCullingTransformVertexprocessing(inner loop)TransformLightingOuter loop isprocessingstripsLightingSingle-PassMulti-PassFigure 9-9. Single-Pass Vs. Multi-Pass 3D Geometry EnginesThe choice of single-pass or multi-pass can have a number of performance implications.For instance, in a multi-pass pipeline, stages that are limited by bandwidth(either input or output) will reflect more of this performance limitation in overallexecution time. In contrast, for a single-pass approach, bandwidth-limitations can bedistributed/amortized across other computation-intensive stages. Also, the choice ofwhich prefetch hints to use are also impacted by whether a single-pass or multi-passapproach is used.9-29
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESmiss
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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Page 270 and 271: MULTICORE AND HYPER-THREADING TECHN
Page 294 and 295: OPTIMIZING CACHE USAGE• Take adva
Page 296 and 297: OPTIMIZING CACHE USAGEHardware pref
Page 298 and 299: OPTIMIZING CACHE USAGEThe non-tempo
Page 300 and 301: OPTIMIZING CACHE USAGE9.5.1.3 Memor
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Page 304 and 305: OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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Page 308 and 309: OPTIMIZING CACHE USAGETimeExecution
Page 310 and 311: OPTIMIZING CACHE USAGEschedule pref
Page 312 and 313: OPTIMIZING CACHE USAGEtime is large
Page 314 and 315: OPTIMIZING CACHE USAGEresource stal
Page 316 and 317: OPTIMIZING CACHE USAGEPrefetchntaDa
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Page 340 and 341: POWER OPTIMIZATION FOR MOBILE USAGE
Page 354 and 355: APPLICATION PERFORMANCE TOOLSThe /f
Page 356 and 357: APPLICATION PERFORMANCE TOOLSTable
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USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUTo
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INSTRUCTION LATENCY AND THROUGHPUTT
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSto
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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