Intel® 64 and IA-32 Architectures Optimization Reference Manual

INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES2.1.4 Intel ® Advanced Memory AccessThe Intel Core microarchitecture contains an instruction cache and a first-level datacache in each core. The two cores share a 2 or 4-MByte L2 cache. All caches arewriteback and non-inclusive. Each core contains:• L1 data cache, known as the data cache unit (DCU) — The DCU can handlemultiple outstanding cache misses and continue to service incoming stores andloads. It supports maintaining cache coherency. The DCU has the following specifications:— 32-KBytes size— 8-way set associative— 64-bytes line size• Data translation lookaside buffer (DTLB) — The DTLB in Intel Core microarchitectureimplements two levels of hierarchy. Each level of the DTLB havemultiple entries and can support either 4-KByte pages or large pages. The entriesof the inner level (DTLB0) is used for loads. The entries in the outer level (DTLB1)support store operations and loads that missed DTLB0. All entries are 4-wayassociative. Here is a list of entries in each DTLB:— DTLB1 for large pages: 32 entries— DTLB1 for 4-KByte pages: 256 entries— DTLB0 for large pages: 16 entries— DTLB0 for 4-KByte pages: 16 entriesAn DTLB0 miss and DTLB1 hit causes a penalty of 2 cycles. Software only paysthis penalty if the DTLB0 is used in some dispatch cases. The delays associatedwith a miss to the DTLB1 and PMH are largely non-blocking due to the design ofIntel Smart Memory Access.• Page miss handler (PMH)• A memory ordering buffer (MOB) — Which:— enables loads and stores to issue speculatively and out of order— ensures retired loads and stores have the correct data upon retirement— ensures loads and stores follow memory ordering rules of the Intel 64 andIA-32 architectures.The memory cluster of the Intel Core microarchitecture uses the following to speedup memory operations:• 128-bit load and store operations• data prefetching to L1 caches• data prefetch logic for prefetching to the L2 cache• store forwarding• memory disambiguation2-13