Intel® 64 and IA-32 Architectures Optimization Reference Manual

64-BIT MODE CODING GUIDELINESinstruction is not the optimal implementation if a 64-bit result is desired. Use theextended registers.For example, the following code sequence loads the 32-bit values sign-extended intothe 64-bit registers and performs a multiply:movsx rax, DWORD PTR[x]movsx rcx, DWORD PTR[y]imul rax, rcxThe 64-bit version above is more efficient than using the following 32-bit version:mov eax, DWORD PTR[x]mov ecx, DWORD PTR[y]imul ecxIn the 32-bit case above, EAX is required to be a source. The result ends up in theEDX:EAX pair instead of in a single 64-bit register.Assembly/Compiler Coding Rule 69. (ML impact, M generality) Use the64-bit versions of multiply for 32-bit integer multiplies that require a 64 bit result.To add two 64-bit numbers in 32-bit legacy mode, the add instruction followed by theaddc instruction is used. For example, to add two 64-bit variables (X and Y), thefollowing four instructions could be used:mov eax, DWORD PTR[X]mov edx, DWORD PTR[X+4]add eax, DWORD PTR[Y]adc edx, DWORD PTR[Y+4]The result will end up in the two-register EDX:EAX.In 64-bit mode, the above sequence can be reduced to the following:mov rax, QWORD PTR[X]add rax, QWORD PTR[Y]The result is stored in rax. One register is required instead of two.Assembly/Compiler Coding Rule 70. (ML impact, M generality) Use the64-bit versions of add for 64-bit adds.9.3.2 CVTSI2SS and CVTSI2SDThe CVTSI2SS and CVTSI2SD instructions convert a signed integer in a generalpurposeregister or memory location to a single-precision or double-precisionfloating-point value. The signed integer can be either 32-bits or 64-bits.In processors based on Intel NetBurst microarchitecture, the 32-bit version willexecute from the trace cache; the 64-bit version will result in a microcode flow fromthe microcode ROM and takes longer to execute. In most cases, the 32-bit versionsof CVTSI2SS and CVTSI2SD is sufficient.9-4