IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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USING PERFORMANCE MONITORING EVENTSMetricBus AccessesUnderway from AllAgents 2Write WC Full (BSQ)Write WC Partial(BSQ)Writes WB Full (BSQ)Table B-5. Performance Metrics - Bus (Contd.)DescriptionAccrued sum of thedurations of entries byall agents on the busDivide by “BusAccesses from AllAgents” to get busrequest latency.Also beware ofdifferent recipes inmask bits for Pentium4 and Intel Xeonprocessors betweenCPUID model fieldvalue of 2 and modelvalue less than 2.The number of write(but neither writebacknor RFO) transactionsto WC-type memory.Number of partialwrite transactions toWC-type memoryThis event mayundercount WC partialsthat originate fromDWord operands.Number of writeback(evicted from cache)transactions to WBtypememory.These writebacks maynot have acorresponding FSB IOQtransaction if 3rd levelcache is present.Event Name or MetricExpressionIOQ_active_entriesEvent Mask ValueRequired1a. ReqA0, ALL_READ,ALL_WRITE, OWN,OTHER, PREFETCH(CPUID model < 2);1b. ReqA0, ALL_READ,ALL_WRITE,MEM_WB, MEM_WT,MEM_WP, MEM_WC,MEM_UC, OWN,OTHER, PREFETCH(CPUID model >= 2).BSQ_allocation 1: REQ_TYPE1|REQ_LEN0|REQ_LEN1|MEM_TYPE0|REQ_DEM_TYPE2: Enable edgefiltering 1 in theCCCR.BSQ_allocation 1: REQ_TYPE1|REQ_LEN0|MEM_TYPE0|REQ_DEM_TYPE2: Enable edgefiltering 1 in theCCCR.BSQ_allocation 1: REQ_TYPE0|REQ_TYPE1|REQ_LEN0|REQ_LEN1|MEM_TYPE1|MEM_TYPE2|REQ_CACHE_TYPE|REQ_DEM_TYPE2: Enable edgefiltering 1 in theCCCR.B-24
USING PERFORMANCE MONITORING EVENTSMetricReads Non-prefetchFull (BSQ)Reads Invalidate Full-RFO (BSQ)UC Reads Chunk(BSQ)UC Reads Chunk Split(BSQ)UC Write Partial(BSQ)Table B-5. Performance Metrics - Bus (Contd.)DescriptionNumber of read(excludes RFOs andHW|SW prefetches)transactions to WBtypememory.Beware of granularityissues with this event.Number of readinvalidate (RFO)transactions to WBtypememoryNumber of 8-bytealigned UC readtransactionsRead requestsassociated with16-byte operands mayunder-count.Number of UC readtransactions spanning8-byte boundaryRead requests mayunder-count if the datachunk straddles 64-byte boundary.Number of UC writetransactionsBeware of granularityissues between BSQand FSB IOQ events.Event Name or MetricExpressionEvent Mask ValueRequiredBSQ_allocation 1: REQ_LEN0|REQ_LEN1|MEM_TYPE1|MEM_TYPE2|REQ_CACHE_TYPE|REQ_DEM_TYPE2: Enable edgefiltering 1 in theCCCR.BSQ_allocation 1: REQ_TYPE0|REQ_LEN0|REQ_LEN1|MEM_TYPE1|MEM_TYPE2|REQ_CACHE_TYPE|REQ_ORD_TYPE|REQ_DEM_TYPE2: Enable edgefiltering 1 in theCCCR.BSQ_allocation 1: REQ_LEN0|REQ_ORD_TYPE|REQ_DEM_TYPE2: Enable edgefiltering 1 in theCCCR.BSQ_allocation 1: REQ_LEN0|REQ_SPLIT_TYPE|REQ_ORD_TYPE|REQ_DEM_TYPE2: Enable edgefiltering 1 in theCCCR.BSQ_allocation 1: REQ_TYPE0|REQ_LEN0|REQ_SPLIT_TYPE|REQ_ORD_TYPE|REQ_DEM_TYPE2: Enable edgefiltering 1 in theCCCR.B-25
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESpred
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GENERAL OPTIMIZATION GUIDELINESIn t
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESmiss
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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OPTIMIZING CACHE USAGE• If a proc
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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Page 354 and 355: APPLICATION PERFORMANCE TOOLSThe /f
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Page 370 and 371: USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTT
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSto
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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