IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURESIntel Core Duo ProcessorIntel Core 2 Duo ProcessorArchitectual StateExecution EngineLocal APICSecond Level CacheBus InterfaceArchitectual StateExecution EngineLocal APICPentium D ProcessorArchitectual State Architectual StateExecution Engine Execution EngineLocal APICLocal APICBus InterfaceBus InterfaceSystem BusArchitectualStatePentium Processor Extreme EditionArchitectualStateArchitectualStateArchitectualStateSystem BusExecution EngineExecution EngineLocal APICLocal APICLocal APICLocal APICBus InterfaceBus InterfaceSystem BusIntel Core 2 Quad ProcessorIntel Xeon Processor 3200 SeriesIntel Xeon Processor 5300 SeriesArchitectual StateArchitectual StateArchitectual StateArchitectual StateExecution EngineExecution EngineExecution EngineExecution EngineLocal APICLocal APICLocal APICLocal APICSecond Level CacheBus InterfaceSecond Level CacheBus InterfaceSystem BusOM19809Figure 2-8. Pentium D Processor, Pentium Processor Extreme Edition,Intel Core Duo Processor, Intel Core 2 Duo Processor, and Intel Core 2 Quad Processor2-42
INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES2.6.1 Microarchitecture Pipeline and MultiCore ProcessorsIn general, each core in a multicore processor resembles a single-core processorimplementation of the underlying microarchitecture. The implementation of thecache hierarchy in a dual-core or multicore processor may be the same or differentfrom the cache hierarchy implementation in a single-core processor.CPUID should be used to determine cache-sharing topology information in aprocessor implementation and the underlying microarchitecture. The former isobtained by querying the deterministic cache parameter leaf (see Chapter 9, “OptimizingCache Usage”); the latter by using the encoded values for extended family,family, extended model, and model fields. See Table 2-8.Dual-CoreProcessorPentium DprocessorPentiumprocessorExtremeEditionIntel Core DuoprocessorIntel Core 2Duoprocessor/Intel Xeonprocessor5100Table 2-8. Family And Model Designations of MicroarchitecturesMicroarchitectureExtendedFamilyFamilyExtendedModelModelNetBurst 0 15 0 3, 4, 6NetBurst 0 15 0 3, 4, 6ImprovedPentium MIntel CoreMicroarchitecture0 6 0 140 6 0 152.6.2 Shared Cache in Intel ® Core Duo ProcessorsThe Intel Core Duo processor has two symmetric cores that share the second-levelcache and a single bus interface (see Figure 2-8). Two threads executing on twocores in an Intel Core Duo processor can take advantage of shared second-levelcache, accessing a single-copy of cached data without generating bus traffic.2.6.2.1 Load and Store OperationsWhen an instruction needs to read data from a memory address, the processor looksfor it in caches and memory. When an instruction writes data to a memory location(write back) the processor first makes sure that the cache line that contains thememory location is owned by the first-level data cache of the initiating core (that is,2-43
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
Page 15 and 16: CONTENTSExample 4-1. Identification
Page 17 and 18: CONTENTSExample 9-8. Using HW Prefe
Page 19 and 20: CONTENTSFigure 9-7. Cache Blocking
Page 21 and 22: CHAPTER 1INTRODUCTIONThe Intel® 64
Page 23 and 24: INTRODUCTION• Chapter 10: Power O
Page 25 and 26: CHAPTER 2INTEL ® 64 AND IA-32 PROC
Page 27 and 28: INTEL® 64 AND IA-32 PROCESSOR ARCH
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Page 75 and 76: CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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OPTIMIZING CACHE USAGE• If a proc
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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APPLICATION PERFORMANCE TOOLSThe /f
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APPLICATION PERFORMANCE TOOLSTable
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APPLICATION PERFORMANCE TOOLSA.1.6.
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSprogra
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APPLICATION PERFORMANCE TOOLSThe Li
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APPLICATION PERFORMANCE TOOLSA.5 IN
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USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUTo
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INSTRUCTION LATENCY AND THROUGHPUTT
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSto
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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