Intel® 64 and IA-32 Architectures Optimization Reference Manual

INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES2.6.1 Microarchitecture Pipeline and MultiCore ProcessorsIn general, each core in a multicore processor resembles a single-core processorimplementation of the underlying microarchitecture. The implementation of thecache hierarchy in a dual-core or multicore processor may be the same or differentfrom the cache hierarchy implementation in a single-core processor.CPUID should be used to determine cache-sharing topology information in aprocessor implementation and the underlying microarchitecture. The former isobtained by querying the deterministic cache parameter leaf (see Chapter 9, “OptimizingCache Usage”); the latter by using the encoded values for extended family,family, extended model, and model fields. See Table 2-8.Dual-CoreProcessorPentium DprocessorPentiumprocessorExtremeEditionIntel Core DuoprocessorIntel Core 2Duoprocessor/Intel Xeonprocessor5100Table 2-8. Family And Model Designations of MicroarchitecturesMicroarchitectureExtendedFamilyFamilyExtendedModelModelNetBurst 0 15 0 3, 4, 6NetBurst 0 15 0 3, 4, 6ImprovedPentium MIntel CoreMicroarchitecture0 6 0 140 6 0 152.6.2 Shared Cache in Intel ® Core Duo ProcessorsThe Intel Core Duo processor has two symmetric cores that share the second-levelcache and a single bus interface (see Figure 2-8). Two threads executing on twocores in an Intel Core Duo processor can take advantage of shared second-levelcache, accessing a single-copy of cached data without generating bus traffic.2.6.2.1 Load and Store OperationsWhen an instruction needs to read data from a memory address, the processor looksfor it in caches and memory. When an instruction writes data to a memory location(write back) the processor first makes sure that the cache line that contains thememory location is owned by the first-level data cache of the initiating core (that is,2-43