Intel® 64 and IA-32 Architectures Optimization Reference Manual

INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURESSoftware can proactively control data access pattern to favor smaller access strides(e.g., stride that is less than half of the trigger threshold distance) over larger accessstrides (stride that is greater than the trigger threshold distance), this can achieveadditional benefit of improved temporal locality and reducing cache misses in the lastlevel cache significantly.Software optimization of a data access pattern should emphasize tuning for hardwareprefetch first to favor greater proportions of smaller-stride data accesses in theworkload; before attempting to provide hints to the processor by employing softwareprefetch instructions.2.2.4.5 Loads and StoresThe Pentium 4 processor employs the following techniques to speed up the executionof memory operations:• speculative execution of loads• reordering of loads with respect to loads and stores• multiple outstanding misses• buffering of writes• forwarding of data from stores to dependent loadsPerformance may be enhanced by not exceeding the memory issue bandwidth andbuffer resources provided by the processor. Up to one load and one store may beissued for each cycle from a memory port reservation station. In order to bedispatched to a reservation station, there must be a buffer entry available for eachmemory operation. There are 48 load buffers and 24 store buffers 3 . These buffershold the µop and address information until the operation is completed, retired, anddeallocated.The Pentium 4 processor is designed to enable the execution of memory operationsout of order with respect to other instructions and with respect to each other. Loadscan be carried out speculatively, that is, before all preceding branches are resolved.However, speculative loads cannot cause page faults.Reordering loads with respect to each other can prevent a load miss from stallinglater loads. Reordering loads with respect to other loads and stores to differentaddresses can enable more parallelism, allowing the machine to execute operationsas soon as their inputs are ready. Writes to memory are always carried out inprogram order to maintain program correctness.A cache miss for a load does not prevent other loads from issuing and completing.The Pentium 4 processor supports up to four (or eight for Pentium 4 processor withCPUID signature corresponding to family 15, model 3) outstanding load misses thatcan be serviced either by on-chip caches or by memory.3. Pentium 4 processors with CPUID model encoding equal to 3 have more than 24 store buffers.2-31