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Intel® 64 and IA-32 Architectures Optimization Reference Manual

Intel® 64 and IA-32 Architectures Optimization Reference Manual

Intel® 64 and IA-32 Architectures Optimization Reference Manual

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INTEL® <strong>64</strong> AND <strong>IA</strong>-<strong>32</strong> PROCESSOR ARCHITECTURESSSE2 instructions are useful for 3D graphics, video decoding/encoding, <strong>and</strong> encryption.2.8.1.4 Streaming SIMD Extensions 3Streaming SIMD extensions 3 add the following:• SIMD floating-point instructions for asymmetric <strong>and</strong> horizontal computation• a special-purpose 128-bit load instruction to avoid cache line splits• an x87 FPU instruction to convert to integer independent of the floating-pointcontrol word (FCW)• instructions to support thread synchronizationSSE3 instructions are useful for scientific, video <strong>and</strong> multi-threaded applications.2.8.1.5 Supplemental Streaming SIMD Extensions 3The Supplemental Streaming SIMD Extensions 3 introduces <strong>32</strong> new instructions toaccelerate eight types of computations on packed integers. These include:• 12 instructions that perform horizontal addition or subtraction operations• 6 instructions that evaluate the absolute values• 2 instructions that perform multiply <strong>and</strong> add operations <strong>and</strong> speed up theevaluation of dot products• 2 instructions that accelerate packed-integer multiply operations <strong>and</strong> produceinteger values with scaling• 2 instructions that perform a byte-wise, in-place shuffle according to the secondshuffle control oper<strong>and</strong>• 6 instructions that negate packed integers in the destination oper<strong>and</strong> if the signsof the corresponding element in the source oper<strong>and</strong> is less than zero• 2 instructions that align data from the composite of two oper<strong>and</strong>s2-49

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